Method and means for encoding and decoding digital data
AssigneeDiscovision Associates
InventorJordan Isailovic
Life of this patent
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Abstract
A data handling system is described for encoding an input digital data waveform by a pulse code modulation technique useful to obtain optimum packing density for a recording medium. The encoding technique selects the binary one state of the input waveform for processing and generates an encoded waveform containing sufficient signal level transition to reconstruct the original input data waveform. The decoding technique examines the transitions present in the retrieved encoded signal and generates decoding indicia sufficient to identify all binary ones in the original digital waveform. A waveform generator recreates the original encoded waveform using selected clocking signals and the decoding indicia.
Claims2
A data handling system of the type employed to encode digital data into a form for optimum packing density on a recording medium, and the digital data being in the form of successive data cell intervals of uniform duration, and each data cell having one of two predetermined signal levels, and any transition between signal levels in the digital data occurring at the start and end of each data cell;
- and of the type employed to decode the encoded digital data and to reconstruct the original form of the digital data using the signals generated during the decoding process;
- the data handling system for encoding the digital data comprising:
- means for generating a clock signal having at least one full cycle corresponding to each data cell interval, and said clock signal having its positive going signal level transition occurring in synchronism with the transition time between adjacent data cells;
- first encoding means responsive to the digital data for providing first encoding indicia representative of one of the two possible signal levels of the data cells;
- second encoding means responsive to the clock signal for providing second encoding indicia identifying each positive going signal level transition of said clock signal;
- and
- means for combining said first encoding indicia and said second encoding indicia into an encoded waveform having signal level transitions occurring at transition times between successive data cells as well as between transition times of successive data cells, and no successively positioned transitions being spaced more than two data cells apart;
- wherein said first encoding means includes:
- first NAND gate means responsive to said digital data to be encoded and to said clock signal for generating a negative going pulse corresponding to each binary one present in said original digital data waveform,
- inverter means responsive to the output of said first NAND gate means for providing an output signal which is the inverted form of the signal from said first NAND gate means and partially delayed with reference to said output of said first NAND gate, and
- second NAND gate means responsive to said output from said first NAND gate and the output of said inverter means for generating a negative going pulse at mid data cell time for each binary one present in said original digital data waveform.
A data handling system of the type employed to encode digital data into a form for optimum packing density on a recording medium, and the digital data being in the form of successive data cell intervals of uniform duration, and each data cell having one of two predetermined signal levels and any transition between signal levels in the digital data occurring at the start and end of each data cell;
- and of the type employed to decode the encoded digital data and to reconstruct the original form of the digital data using the signals generated during the decoding process;
- the data handling system for encoding the digital data comprising:
- means for generating a clock signal having at least one full cycle corresponding to each data cell interval, and said clock signal having its positive going signal level transition occurring in synchronism with the transition time between adjacent data cells;
- first encoding means responsive to the digital data for providing first encoding indicia representative of one of the two possible signal levels of the data cells;
- second encoding means responsive to the clock signal for providing second encoding indicia identifying each positive going signal level transition of said clock signal;
- and
- means for combining said first encoding indicia and said second encoding indicia into an encoded waveform having signal level transitions occurring at transition times between successive data cells as well as between transition times of successive data cells, and no successively positioned transitions being spaced more than two data cells apart;
- wherein said second encoding means includes:
- inverter means responsive to said clock signal for providing an output signal which is the inverted form of said clock signal and partially delayed with reference to said clock signal, and
- first NAND gate means responsive to said clock signal and the output of said inverter means for generating a negative going pulse at start of data cell time for each positive going transition in said clock signal.
Dependencies are inferred from the claim text.