Method and apparatus for testing electronic devices

A method of testing an electronic device comprising the steps of:

• generating a pulse of predetermined shape and duration;
• comparing said pulse with at least a first feedback signal;
• generating an error voltage in response to said comparison;
• sinking current passing through a device at a rate controlled by said error voltage;
• generating said first feedback signal as an indication of the current magnitude flowing through the device;
• measuring the voltage across the device at a predetermined time after the beginning of said pulse;
• determining whether the voltage across the device is above or below a predetermined limit;
• generating a second feedback signal to said comparator for indicating whether said predetermined limit has been exceeded;
• and
• decreasing said error voltage appreciably in said comparator when said second feedback signal indicates that the voltage across the device is below the predetermined limit.

A method of testing a surge protector comprising the steps of:

• (a) generating a voltage pulse having an initial negative peak voltage followed by an exponentially decaying waveform;
• (b) summing said inverted voltage pulse with a feedback voltage to form a first summed voltage;
• (c) inverting said summed voltage to form an error voltage;
• (d) coupling said error voltage to the input of a Darlington array amplifier to sink current from a voltage source through a surge protector;
• (e) transforming the magnitude of current flowing through said surge protector to a proportional magnitude of voltage to produce said feedback voltage;
• (f) detecting the voltage across the surge protector at a predetermined time during the duration of said voltage pulse;
• (g) comparing said voltage across the surge protector to a predetermined voltage to produce a pass/fail signal;
• (h) inverting the voltage across said voltage source to form an inverted supply voltage;
• (i) attenuating said inverted supply voltage to form an attenuated, inverted supply voltage;
• (j) summing said attenuated, inverted supply voltage to said surge protector voltage to form a second summed voltage;
• and
• (k) decreasing said error voltage if said second summed voltage is less than a reference potential and if said predetermined time has elapsed.