Digital signal conversion circuit
AssigneeGTE Laboratories Incorporated
InventorJun-ichi Sano
Life of this patent
Estimating the term…
Abstract
Circuit for converting input signals at TTL voltage levels to output signals at voltage levels for use with MOS logic circuits. The circuit employs an arrangement of NMOS FET's. Six FET's are arranged in pairs to form three inverters. Another FET is connected in series between the input terminal and different portions of the first and second of the three inverters. The output of the second inverter is fed back to the gate electrode of one of the FET's of the first inverter and to the gate electrode of the series connected FET. The output of the second inverter is also applied to the third inverter. The excursion between voltage levels representing logic 1 and logic 0 at the output of the third inverter is greater than the excursion between voltage levels representing logic 1 and logic 0 at the input to the circuit.
Claims13
A digital signal conversion circuit comprising
- an input terminal for receiving input signals having a first voltage condition or a second voltage condition;
- a first field effect transistor connected in series between the input terminal and a first connection point;
- a second field effect transistor connected between the first connection point and a point of reference potential;
- a third field effect transistor connected between a source of operating potential and the first connection point;
- a fourth field effect transistor connected between a second connection point and the point of reference potential;
- and
- a fifth field effect transistor connected between the source of operating potential and the second connection point;
- the first connection point being connected to the gate of the fourth field effect transistor;
- the second connection point being connected to the gate of the first field effect transistor and to the gate of the second field effect transistor;
- said first field effect transistor being operable in response to a first voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a high impedance condition thereby producing a third voltage condition at the second connection point;
- said first field effect transistor being operable in response to a second voltage condition at the input terminal to produce a voltage at the first connection point biasing the fourth field effect transistor to a low impedance condition thereby producing a fourth voltage condition at the second connection point;
- and
- said first and second field effect transistors being biased to conduction in response to said third voltage condition at the second connection point and being biased to nonconduction in response to said fourth voltage condition at the second connection point.
A digital signal conversion circuit comprising
- an input terminal for receiving input signals having a first voltage condition or a second voltage condition;
- a first field effect transistor of the depletion type connected in series between the input terminal and a first connection point;
- a second field effect transistor of the enhancement type connected between the first connection point and a point of reference potential;
- a third field effect transistor of the depletion type connected between a source of operating potential and the first connection point;
- a fourth field effect transistor of the enhancement type connected between a second connection point and the point of reference potential;
- a fifth field effect transistor of the depletion type connected between the source of operating potential and the second connection point;
- the gates of the third and fourth field effect transistors being connected to the first connection point;
- the gates of the first, second, and fifth field effect transistors being connected to the second connection point.
- whereby when a first voltage condition is present at the input terminal a third voltage condition is produced at the second connection point and when a second voltage condition is present at the input terminal a fourth voltage condition is produced at the second connection point.
Dependencies are inferred from the claim text.