Digital loop synchronization circuit

A synchronization circuit for use in a digital communication system, said system having a plurality of serially interconnected stations, said stations arranged for intercommunication via a digital data channel, said channel divided into frames with each frame having n bit positions, each M.sup.th frame having at least one frame bit on said one channel

• said synchronization circuit comprising
• a FIFO register having bit length Mn, said FIFO arranged for insertion in said digital channel between any two of said stations so that said bits of each said frame pass from an input to an output of said FIFO,
• a first clock for controlling bits into said FIFO one bit at a time,
• a second clock for controlling bits out of said FIFO one bit at a time,
• means for comparing the frame bit of each frame at the output of said FIFO with a subsequent frame bit on said digital channel, and
• means responsive to each mismatch between said compared bits for inhibiting the clocking one bit out of said FIFO while one bit is clocked into said FIFO.

An adaptive synchronization circuit for use in a digital communication system, said system having m serially interconnected data units, said units arranged for intercommunication via a digital data channel, said channel divided into frames with each frame having n bits positions, each said frame having at least one frame bit placed on said data channel,

• said synchronization circuit comprising
• a FIFO register having bit length at least n-m, said FIFO arranged for insertion in said digital channel between any two of said units so that said bits of each said frame pass from an input to an output of said FIFO,
• means for clocking bits into said FIFO,
• means for clocking the bits out of said FIFO,
• means for comparing the frame bit of each frame at the output of said FIFO with a subsequent frame bit on said digital channel, and
• means responsive to each mismatch between said compared bits for inhibiting the clocking of one bit out of said FIFO.

A synchronization circuit for use in a digital communication system, said system having a plurality of serially interconnected stations, said stations arranged for intercommunication via a digital data channel, said channel divided into frames with each frame having n bit positions,

• said synchronization circuit comprising means for generating a frame synchronizing bit and for placing said synchronizing bit in each frame on said digital data channel
• at least two FIFO registers, each FIFO register arranged for insertion in said digital channel between any two of said stations so that said bits of each said frame pass from an input on an output of at least one of said FIFO registers, and said frame synchronization bits pass from an input to an output of a second one of said registers,
• a first clock for controlling said bits into said FIFO registers one bit at a time
• a second clock for controlling said bits out of said FIFO registers one bit at a time
• means for comparing the frame synchronization bit of a particular frame at the output of said second FIFO register with a generated frame synchronizing bit of a next frame on said digital data channel, and
• means responsive to a mismatch between said compared bits for inhibiting said second clock so as to inhibit the clocking of one bit out of said FIFO registers while still allowing one bit to be clocked into said FIFO registers by said first clock.