Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits

A structure for the generation and detection of charge packets comprising:

• a charge-coupled device including a semiconductor substrate of a first conductivity type material, at least three electrodes in a linear arrangement proximate to and in electrical contact with said substrate, and a region of second conductivity type material located in said substrate proximate to a first one of said electrodes, said region of second conductivity type material being a source of electrical charge carriers, said first one of said electrodes being a barrier electrode connected to a source of electrical potential for creating a potential level barrier in said substrate under said first electrode,
• a logic and control circuit for producing digital signals,
• a digital-to-analog converter circuit having an input connected to the output of said logic and control circuit and an output connected to a second one of said electrodes of said charge-coupled-device, said digital-to-analog converter circuit producing an analog signal having a value representative of a digital signal value from said logic and control circuit for creating a potential well in said substrate under said second electrode, said potential well having a depth proportional to said analog signal,
• and a trigger comparator circuit having an input connected to said region of second conductivity type material on said substrate and an output connected to said logic and control circuit, said trigger comparator circuit applying an electrical potential level on said region of second conductivity type material to produce electrical charge carriers which transfer over said potential level barrier and fill said potential well under said second electrode to create a charge packet proportional to said value of said analog and digital signals.