Operational amplifier with offset compensation

#The present invention relates to offset voltage compensation for operational amplifiers, particularly those utilizing FET (field-effect transistor) devices for switching functions.

#The input offset voltage of an operational amplifier is the voltage which must be applied between its input terminals in order to bring the output voltage to a predetermined reference level when there is no signal input. This offset voltage is a generally known error characteristic of operational amplifiers which is due to an uncontrollable mismatch of components.

#For certain applications of operational amplifiers, it is particularly important to eliminate errors which result from uncompensated input offset voltages. Such is the case, for example, for operational amplifiers which are used for charge redistribution codecs in telephone communications, where it is generally desirable to maintain the effects of each internal source of error to less than one-tenth LSB (least significant bit). A particular charge-redistribution codec is described, for example, in Suarez et al., "An ALL-MOS Charge-Redistribution A/D Conversion Technique," 1974, IEEE Internat. Solid-State Circuits Conference, p. 194, U.S.A.

#FIGS. 1, 2, and 3 of the drawings show an operational amplifier with an offset voltage compensating circuit arrangement typical of the prior art as discussed above and schematically illustrate the circuit in the reset, transition, and trasmit conditions, respectively; and

#FIGS. 4, 5, and 6 show an operational amplifier with an offset voltage compensation circuit arrangement in accordance with a preferred embodiment of the present invention and schematically illustrate the circuit in the reset, transition and transmit conditions, respectively.

#A preferred embodiment of the novel apparatus is illustrated in FIGS. 4, 5, and 6 of the drawings. The apparatus is an operational amplifier circuit of the type which may be used, for example, as a subcircuit in a larger and more complex integrated circuit.

#Referring now to the FIGS. 4, 5, and 6, the circuit 10 includes an operational amplifier 12 having a signal input terminal 14, a feedback input terminal 16, a single output terminal 18, and a feedback loop 20 between the feedback input terminal 16 and the output terminal 18. A feedback shunt switch 22 is provided in the feedback loop 20 to permit the loop 20 to be opened. A feedback capacitor 24 with one side connected between the feedback shunt switch 22 and the feedback input terminal 16 has its other side connected to a double-throw feedback reset switch 26 which can selectively switch to a reference potential 28, such as ground potential, or to the output terminal 18. An input capacitor 30 is connected between the signal input terminal 14 and a double-throw signal source switch 31. The switch 31 can selectively connect the input capacitor 30 to the reference potential or to the signal input source 32. An input reset switch 34 is connected between the signal input terminal 14 and the reference potential 28. The switches 22, 26, 34 are all FET devices, such as MOS transistor switches.

#In the reset condition of the circuit 10, as shown in FIG. 4, the feedback capacitor 24 is charged to the input offset voltage, while the input terminal 14 is grounded and the input capacitor 30 is discharged.