Bipolar inverter and NAND logic circuit with extremely low DC standby power

A logic circuit comprising:

• a first pair of bipolar switchable transistors connected in series a first region of one of said first pair being connected to a given potential,
• a second pair of bipolar switchable transistors which are the complements of said first pair of transistors connected in parallel, first regions of which are connected to a potential different from said given potential and second regions of which are connected to a second given region of another of said first pair, a first region of said another of said first pair being connected to a second region of said one of said first pair, an output terminal connected to said second regions of said second pair of transistors and to said second region of said another of said first pair, a first input terminal connected to a third region of said one of said first pair of transistors and to a third region of one of said second pair input terminal connected to a third region of said another of said first pair of transistors and to a third region of another of said second pair of transistors,
• a source of standby current of a first polarity connected to each of said third regions of said first pair of transistors for maintaining said transistors in a conductive state when rendered conductive by a signal applied to said first and second inputs terminals,
• a source of standby current of a second polarity connected to each of said third regions of said second pair of transistors for maintaining said transistors in a conductive state when rendered conductive by another signal applied to said first and second input terminals,
• means connected between each of said sources of standby current and said input terminals for shunting said sources of standby current of said first and second polarity to said given potential and to the level of said signal, respectively, when said signal or said another signal applied to any of said transistors of said first and second pairs of transistors renders any of them nonconductive, and, means connected in parallel with each said means for shunting for augmenting said standby current of one polarity and said standby current of second polarity when the application of said signal or said another signal to said third regions of said first and second pairs of transistors renders any of said transistors conductive.