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US 4,305,134 AGranted
Automatic operand length control of the result of a scientific arithmetic operation
AssigneeHoneywell Information Systems Inc.
InventorsThomas F. Joyce, Richard A. Lemay, William E. Woods
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Abstract
Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.
Claims6
A processing system comprising:
- a random access memory having a first and second plurality of address locations, each having an upper portion and a lower portion for storing operand mantissas in said first plurality of address locations and for storing binary ZERO bits in said lower portion of said second plurality of address locations;
- register means for generating a plurality of length signals indicative of the length of each of said operand mantissas;
- and
- addressing means coupled to said register means and said random access memory being responsive to one of said plurality of length signals in a first state for selecting one of said operand mantissas from said upper and said lower portions of one of said first plurality of address locations, and being responsive to said one of said plurality of length signals in a second state for selecting said one of said operand mantissas from said upper portion of said one of said first plurality of address locations and said lower portion of a corresponding one of said second plurality of address locations for transfer of said operand mantissas to an output.
1 more element
Dependencies are inferred from the claim text.