US 4,305,133 AGranted

Recursive type digital filter

AssigneeHitachi, Ltd.

InventorsEiichi Amada, Makoto Ohnishi, Hiroshi Kuwahara

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Abstract

A recursive type digital filter receiving a digital input signal x(n) having a plurality of bits and delivering a ditial output signal y(n) satisfying the following equation, ##EQU1## where n indicates a natural number, M and N orders of time lag in the signal transference, a.sub.k and b.sub.k coefficients defined by a filter characteristic, a.sub.M and b.sub.N b being coefficients which are not equal to zero, comprises an output control circuit for delivering a digital signal indicating a positive or negative limit value in place of the digital output signal y(n) when the amplitude of the signal y(n) exceeds an allowable value. In combination with this output control circuit, the filter also utilizes a feedback signal for calculation purposes which feedback signal has its amplitude reduced from that of y(n) by a predetermined ratio. Further, an arrangement is provided for clearing registers of filter when necessary to prevent overflow oscillation.

Claims11

Dependent claims

A recursive type digital filter comprising:

an arithmetic unit having an input and output means for delivering from the output means thereof a digital signal y(n) shown by a formula, ##EQU9## where n represents a natural number, N and M are orders representing a delay of signal transmission, and a.sub.k and b.sub.k are coefficients with a.sub.M, b.sub.N .noteq.0;
first means connected to said input means for applying digital signals x(n-k) to said arithmetic unit, said digital signal x(n-k) having a plurality of bits and including at least an input digital signal x(n) applied thereto at a predetermined sampling period;
second means connected between the output means and the input means of said arithmetic unit for feeding back at least a digital signal y(n-k) to the input means of said arithmetic unit, said digital signal y(n-k) having a plurality of bits, said second means including a signal delaying means for delaying a digital signal delivered from the output means of said arithmetic unit by at least one sampling period to feed the so delayed signal back to the input means of said arithmetic unit;
a filter output terminal coupled to the output means of said arithmetic unit for delivering a digital signal y(n) as the output of the filter;
third means connected to said arithmetic unit for detecting that the amplitude of said digital signal y(n) to be applied to said filter output terminal exceeds a predetermined value;
fourth means, connected between said filter output terminal and said third means and controlled by said third means, for sending to said filter output terminal a digital signal indicating either one of positive and negative limit values in place of said digital signal y(n) from said arithmetic unit;
and
fifth means connected to said arithmetic unit for detecting that the value of said digital signal to be applied from said arithmetic unit to said second means exceeds the data capacity of said signal delaying means, at least the contents of said signal delaying means and the contents of the output means of said arithmetic unit being zero-cleared by means of the output signal of said fifth means.

5 more elements

A recursive type digital filter comprising:

an arithmetic unit having an input and output means for delivering from the output means thereof first and second digital signals, said first digital signal being shown by a formula, ##EQU10## where n represents a natural number, N and M are orders representing a delay of signal transmission, and a.sub.k and b.sub.k are coefficients with a.sub.M, b.sub.N .noteq.0, and said second digital signal having an amplitude which is reduced from that of said first signal by a predetermined ratio;
first means connected to said input means for applying digital signals x(n-k) to said arithmetic unit, said digital signal x(n-k) having a plurality of bits and including at least an input digital signal x(n) applied thereto at a predetermined sampling period;
second means connected between the output means and the input means of said arithmetic unit for feeding back said second digital signal as said digital signal y(n-k) to the input means of said arithmetic unit, said digital signal y(n-k) having a plurality of bits;
a filter output terminal coupled to the output means of said arithmetic unit for delivering said first digital signal as the output of the filter;
third means connected to said arithmetic unit for detecting that the amplitude of said first digital signal to be applied to said filter output terminal exceeds a predetermined value;
and
fourth means, connected between said filter output terminal and said third means and controlled by said third means, for sending to said filter output terminal a digital signal indicating either one of positive and negative limit values in place of said first digital signal from said arithmetic unit, while keeping the value of said second digital signal to be fed back to the input means of said arithmetic means unchanged by the limmit values.

4 more elements

Dependencies are inferred from the claim text.