Decoder circuitry for selectively activating loads

In an automatic garage door operator using a decoder system having comparison means for comparing a received signal with a local code signal, with said comparison means providing a matched signal upon coincidence between the received and local code signals, the improvement comprising:

• oscillator means for generating a series of clock pulses independently of said signals;
• output latch means for activating a load;
• means for initially setting said output latch to activate the load in response to at least one matched signal;
• and
• reset means for clearing said latch means only after a predetermined time delay defined by the generation of a given number of successive clock pulses from said oscillator without an intervening matched signal from said comparison means.

In a decoder circuit for selectively activating an external load depending on the contents of a repeatedly received digital word code defined by a series of pulses having different characteristics, said decoder including comparison means for comparing on a pulse-by-pulse basis the received code with an internally generated local code, the improvement comprising:

• local code generator means including a counter for sequentially providing a plurality of count signals;
• oscillator means for providing a plurality of clock signals;
• accumulator means coupled to said counter means, operative to store a plurality of matched signals therein, each of said matched signals being a predetermined count signal from the counter means which is generated upon coincidence of all of the pulses in the local and received codes;
• output latch means coupled to said accumulator means, operative to activate a load in response to an output signal from said accumulator means;
• reset means having a clock input and a reset input, said clock input being coupled to said oscillator means and said reset input being coupled for receipt of said predetermined count signal from said counter means, said reset means having an output coupled to a reset input of the accumulator means wherein said reset means clears said accumulator means after receiving a predetermined number of clock pulses unless reset beforehand by said predetermined count from said counter indicating a match between the local and received codes;
• and
• said accumulator means being operative to provide said output signal to the latch to activate the load upon receipt of given plurality of matched signals before being reset.

In a decoder circuit having comparison means for comparing a received digital code signal with an internally generated local digital code signal on a pulse-by-pulse basis, with said circuit providing an output signal for activating a load if said received and local codes coincide, wherein the improvement comprises:

• transistor means having an input coupled to the output of said comparison means;
• a resistor-capacitor network coupled to the output of said transistor means;
• reference voltage means for providing a reference voltage and
• a second comparator having one input coupled to the output of the network and its other input coupled to said reference voltage means wherein said comparison means provides an error signal of a time duration equal to the difference between the pulse widths of the received and local codes, said error signal causing said transistor means to charge the capacitor and provide a voltage level to said second comparator, with said second comparator providing an output signal signifying an untolerated mismatch if said voltage level exceeds the reference voltage level.