Phase locked loop clock synchronizing circuit with programmable controller

A clock pulse generator synchronizing arrangement comprising:

• digitally controllable clock oscillator means for generating clock output signals;
• and
• phase comparator means for generating a phase signal indicative of the phase difference between said clock output signals and reference signals;
• characterized in that
• said arrangement comprises programmable processor means responsive to said phase signal for generating and transmitting control signals to said clock oscillator means;
• means at said clock oscillator means for generating echo signals corresponding to said control signals received at said clock oscillator means;
• and
• means for transmitting said echo signals to said programmable processor means;
• said programmable processor means being responsive to a mismatch condition between said echo signals and said control signals to prevent said clock oscillator means from responding to said control signals.

A clock pulse generator synchronizing arrangement comprising:

• digitally controlled clock oscillator means responsive to control signals for generating clock output signals of a frequency defined by said control signals;
• and
• phase comparator means for generating a phase signal indicative of the phase difference between said clock output signals and reference signals;
• characterized in that
• said arrangement comprises duplicated processor means, each of said duplicated processor means responsive to said phase signal to generate said control signals;
• means for transferring said control signals to said clock oscillator means;
• and
• means operative in response to said control signals for inhibiting the transfer of said control signals to said clock oscillator means if said control signals from one of said duplicated processor means are not identical to control signals from other of said duplicated processor means.

A clock pulse generator synchronizing arrangement comprising:

• a master clock oscillator for generating master clock signals and a slave clock oscillator for generating slave clock signals, said slave oscillator responsive to an analog signal and a digital control word to vary frequency of said slave clock signals;
• an analog phase-lock means for generating said analog signal to control said slave oscillator such that the frequency of said slave clock signals equals the frequency of said master clock signal;
• characterized in that
• said arrangement comprises means responsive to said analog signal to compute said digital control word such that said analog signal is adjusted to a predetermined value.

A clock pulse generating arrangement comprising:

• a clock oscillator means for generating clock output signals;
• phase comparator means for generating a phase signal indicative of the phase difference between said clock output signals and reference signals;
• characterized in that
• said arrangement further comprises:
• pulse phase shift means for introducing a phase shift in said reference signals prior to the application thereof to said phase comparator means;
• and
• control means responsive to said phase signal for generating control signals defining said phase shift;
• said phase shift means being responsive to said control signals for introducing said phase shift.