US 4,304,964 A · Variable frame length data converter for a speech synthesis circuit

Abstract

A speech synthesis circuit is provided with a variable frame length data converter and the speech synthesizer is preferably integrated on an integrated circuit chips. The variable frame length data converter reduces the amount of data required to synthesizer human speech at a given quality level. Preferably, a full frame of data includes, a pitch parameter, an energy parameter, a repeat bit and a plurality of speech coefficients. Each parameter or coefficient has a preselected length, but each frame has a variable number of parameters or coefficients associated therewith. The parameters and coefficients are encoded and a particular code of the pitch parameter indicates that the speech is to be unvoiced. An unvoiced frame includes fewer coefficients that a voiced frame and the converter detects this particular pitch parameter and automatically sets the unsent coefficients to zero. The converter also detects the state of the repeat bit for controlling the synthesizing to use the coefficients received during the previous frame as the coefficient to be used to generate speech in response to the present frame. In this embodiment, when the repeat bit comes up, new pitch and energy parameters are inputted therewith. Further, the converters preferably detects particular codes in the energy parameter for determining when a pause occurs or when the last frame of data has been sent.

Claims20

Dependent claims

A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of the frames including a plurality of encoded parameters, the method comprising the steps of:

(a) generating a frame timing signal indicative of the start of a new frame of data;
(b) generating a parameter timing signal indicative of the start of a new encoded parameter;
(c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal;
(d) testing the first encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said first encoded parameter is a preselected code;
and
(e) generating said inhibit signal until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal if said first encoded parameter is in the preselected code.

3 more elements

(a) generating a frame timing signal indicative of the start of a new frame of data;
(b) generating a parameter timing signal indicative of the start of a new encoded parameter;
(c) loading encoded parameters from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal;
(d) testing the second encoded parameter loaded into said input register after the occurrence of said frame timing signal to determine whether said second encoded parameter is a preselected code;
and
(e) generating said inhibit signal:
(i) after a plurality of said encoded parameters have been inputted to said speech synthesis circuit via said input register;
and
(ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.

6 more elements

A method of decoding encoded variable frame length data being coupled to a speech synthesis circuit from a memory means storing said encoded variable frame length data, each frame including at least one encoded parameter and a majority of frames including a plurality of encoded parameters and a repeat bit, the method comprising the steps of:

(a) generating a frame timing signal indicative of the start of a new frame of data;
(b) generating a parameter timing signal indicative of the start of a new encoded parameter;
(c) loading a new encoded parameter from said memory means into an input register associated with said speech synthesis circuit in timed relation with said parameter timing signal unless inhibited by an inhibit signal;
(d) testing the state of said repeat bit;
and
(e) when said repeat bit is of a preselected state, generating said inhibit signal:
(i) after at least two of said encoded parameters have been inputted to said speech synthesis circuit via said input register;
and
(ii) until the next frame of data is ready to be inputted into said input register as determined by the occurrence of said frame timing signal.

6 more elements

A speech synthesis system comprising:

(a) memory means for storing variable frame length data, said variable frame length data including encoded variable length speech parameters representative of pitch, energy and filter coefficients, each frame of said variable frame length data including at least one encoded parameter;
(a) control means coupled to said memory means for selectively addressing said variable frame length data;
(c) speech synthesis means coupled to said memory means for converting said encoded variable length speech parameters into analog signals representative of human speech, said speech synthesis means including:
a parametric data converter comprising:
(i) timing means for generating a frame timing signal indicative of the start of a frame of data as well as parameter timing signals indicative of the start of each encoded parameter in a frame:
(ii) an input register, coupled to said memory means, whose length is sufficient to accommodate the longest of said encoded parameters;
(iii) an input register control means coupled to said input register and said timing means for controlling the inputting of said encoded speech parameters into said input register in timed relationship with said parameter timing signals generated by said timing means, in the absence of an inhibit signal, and for prohibiting the inputting of said encoded speech parameters into said input register in the presence of an inhibit signal;
(iv) first circuit means, coupled to said input register and said timing means, for testing a first encoded parameter in a frame of data to determine whether said frame contains only one encoded parameter, said first encoded parameter having at least one preselected code indicating said frame of data contains only one encoded parameter;
and
(v) second circuit means, coupled to said first circuit means and said timing means for generating said inhibit signal in response to said first circuit means detecting said at least one preselected code, said inhibit signal being generated until said timing means indicates the start of a next frame of data;
and
(d) audio means for converting said analog signals representative of human speech into audible sounds.

9 more elements

Dependencies are inferred from the claim text.

Variable frame length data converter for a speech synthesis circuit

Life of this patent

Variable frame length data converter for a speech synthesis circuit

Life of this patent

Abstract

Claims20