Data processing system with error checking
AssigneeInternational Computers Limited
InventorDavid J. Hunt
Life of this patent
Estimating the term…
Abstract
A data processing system is disclosed consisting of a plurality of data processing elements and parity processing elements. The parity processing elements hold parity bits for checking the contents of the internal registers and internal stores of the data processing elements and perform substantially the same operations on the parity bits as the data processing elements perform on the data. However, some of these operations may invalidate the parity bits. In particular, the carry result from an addition operation is not always valid. A parity valid logic circuit is therefore provided to generate a signal which indicates whether the parity bits from all the parity processing elements are valid, and hence whether the parity check performed using these parity bits is valid.
Claims7
A data processing system comprising:
- (a) a plurality of substantially identical data processing elements each of which includes
- (i) a data store having a plurality of individually addressable locations and
- (ii) processing logic connected to the data store;
- (b) a check code processing element including
- (i) a check code store having a plurality of individually addressable locations, each location in the check code store holding a check code for the data in the set of locations in the data stores having the same address, and
- (ii) processing logic connected to the check code store;
- (c) means for applying an address signal in parallel to all the data stores and also to the check code store, to thereby address a location in each of said stores;
- (d) means for applying a single stream of control signals in parallel to all the data processing elements and also to the check code processing element to cause all the elements to perform the same operation in parallel, and thereby to produce respective output signals;
- (e) checking means connected to the data processing element and also to the check code processing element, for combining the output signals of the data processing element and check code processing element to produce a signal indicative of whether there is an error in the output signals from the data processing elements;
- (f) logic circuit means connected to receive said control signals, for deducing from said control signals whether the output signal from the check code processing element is a valid check code;
- and
- (g) means responsive to the logic circuit means, for suppressing the output signal from the checking means in the event that the output from the check code processing element is not a valid check code.
Dependencies are inferred from the claim text.