Memory present apparatus

A memory module board for providing any one of a number of like segments of addressable memory space within a memory subsystem, said memory module board comprising:

• a number of rows of addressable memory chips for providing a plurality of addressable storage locations defining a segment;
• range switch selection means connected to receive a set of signals corresponding to a first portion of a memory address coded to specify said memory segment to be accessed, said range switch selection means being selectively positioned in accordance with the location of said module board within said subsystem to modify said set of signals for providing a set of coded signals designating one of said segments;
• circuit means connected to receive said set of coded signals from said range switch means and being operated to logically combine said coded signals to generate a resulting signal;
• register means for storing a second selected portion of said memory address coded to specify the row of chips of one of said plurality of storage locations;
• memory present circuit means coupled to said circuit means and to said register means, said memory present circuit means being conditioned by said resulting signal and said another portion of said plurality of address signals to generate a memory present signal for enabling the accessing of a storage location within a specified one of said rows of said one segment.

A memory subsystem constructed to facilitate expansion and repair, said subsystem being connected to a bus in common to a processing unit and comprising:

• a plurality of memory module boards, each board being identical in construction and having identical address connections for receiving a plurality of address signals from said bus specifying a location within said subsystem to be accessed, each board including a memory section and control section;
• each said memory section including a number of rows of addressable memory chips for providing a plurality of storage locations, each row corresponding to a different increment of a memory segment;
• and,
• said control section including:
• manually selectable range switch being connected for receiving a first portion of said plurality of address signals coded to specify the segment and said range switch being selectively positioned in accordance with the placement of said module board within said subsystem to generate coded signals specifying a desired segment in response to said first portion;
• circuit means connected to receive said coded signals and being operated to logically combine said coded signals to generate a resulting signal;
• a register for receiving another portion of said plurality of address signals coded for specifying said increment of said segment to be accessed;
• and,
• memory present circuit means coupled to said circuit means and to said register, said memory present circuit means being conditioned by said resulting signal and said another portion of said plurality of address signals to generate a memory present signal for enabling access to a location in said increment of the segment specified by the positioning of said range switch.