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US 4,303,938 AGranted
Pattern generator for simulating image generation
AssigneeThe United States of America as represented by the Secretary of the Navy
InventorsHerbert Berke, John H. Allen
Life of this patent
Estimating the term…
Abstract
A pattern generator for simulating image generation is disclosed which pets the testing of wide angle, non-programmed visual display systems including, for example, a 360.degree. non-programmed visual display system. The program generator produces a pair of composite signals, the first of which may be utilized by an annular projector to project upon a screen a sawtooth waveform pattern, and the second of which may be utilized by the annular projector to project upon the screen a checkerboard pattern so as to facilitate the testing of wide angle visual display systems.
Claims21
A pattern generator for simulating image generation comprising, in combination:
- clock generating means having an output for producing a clock signal, said clock signal having a plurality of clock pulses;
- pulse shaping means having a quintet of inputs effectively connected to the output of said clock generating means and a quintet of outputs for providing, in response to each of the clock pulses of said clock signal, a quintet of data pulses, each of which has a predetermined pulse width;
- gating means, having a clock input connected to the output of said clock generating means, a quintet of data inputs effectively and respectively connected to the quintet of outputs of said pulse shaping means and an output adapted for passing, in sequence, a set of the first of said quintet of data pulses, a set of the second of said quintet of data pulses, a set of the third of said quintet of data pulses, a set of the fourth of said quintet of data pulses, and a set of the fifth of said quintet of data pulses;
- timing means having an input connected to the output of said gating means and an output adapted for delaying, in sequence, each set of said quintet of data pulses passed by said gating means for a first time interval, a second time interval, and a third time interval so as to form at the output thereof a first composite signal;
- and
- checkerboard pattern generating means having an input connected to the output of said clock generating means and an output for providing at the output thereof a second composite signal.
3 more elements
A signal generating system comprising in combination:
- a master clock generator having an output;
- a divider having an input connected to the output of said master clock generator and an output;
- a first counter having a clock input effectively connected to the output of said divider and an output;
- a second counter having a clock input connected to the output of said first counter and an output;
- a first flipflop having a trigger input effectively connected to the output of said second counter, a Q output and a Q output;
- a shift register having a clock input effectively connected to the output of said first counter, an S.sub.1 input connected to the Q output of said first flipflop, a reset input connected to the Q output of said first flipflop, an S.sub.0 input connected to the Q output of said first flipflop, a data input, and Q.sub.0, Q.sub.1, Q.sub.2, and Q.sub.3 outputs;
- a NOR gate having first, second, third, and fourth inputs respectively connected to the Q.sub.0, Q.sub.1, Q.sub.2, and Q.sub.3 outputs of said shift register, and an output connected to the data input of said shift register;
- a first pulse shaper having an input effectively connected to the output of said divider and an output;
- a second pulse shaper having an input effectively connected to the output of said divider and an output;
- a third pulse shaper having an input effectively connected to the output of said divider and an output;
- a fourth pulse shaper having an input effectively connected to the output of said divider and an output;
- a fifth pulse shaper having an input effectively connected to the output of said divider and an output;
- a first AND gate having a first input connected to the output of said NOR gate, a second input connected to the output of said first pulse shaper, and an output;
- a second AND gate having a first input connected to the Q.sub.0 output of said shift register, a second input connected to the output of said second pulse shaper, and an output;
- a third AND gate having a first input connected to the Q.sub.1 output of said shift register, a second input connected to the output of said third pulse shaper, and an output;
- a fourth AND gate having a first input connected to the Q.sub.2 output of said shift register, a second input connected to the output of said fourth pulse shaper, and an output;
- a fifth AND gate having a first input connected to the Q.sub.3 output of said shift register, a second input connected to the output of said fifth pulse shaper, and an output;
- a first OR gate having first, second, third, fourth, and fifth inputs respectively connected to the outputs of said first, second, third, fourth, and fifth AND gates;
- a first delay timer having an input connected to the output of said OR gate, and an output;
- a second delay timer having an input connected to the output of said OR gate, and an output;
- a third delay timer having an input connected to the output of said OR gate, and an output;
- a sixth pulse shaper having an input connected to the output of said delay timer, and an output;
- a seventh pulse shaper having an input connected to the output of said second delay timer, and an output;
- an eighth pulse shaper having an input connected to the output of said third delay timer, and an output;
- a second OR gate having first, second, and third inputs respectively connected to the outputs of said sixth, seventh, and eighth pulse shapers;
- a third counter having a clock input effectively connected to the output of said divider, and an output;
- a second flipflop having a trigger input connected to the output of said counter, a Q output, and a Q output;
- a ninth pulse shaper having an input connected to the output of said divider, and an output;
- an oscillator having an input connected to the output of said ninth pulse shaper, and an output;
- a third flipflop having a trigger input connected to the output of said oscillator, a Q output, and a Q output;
- a sixth AND gate having a first input connected to the Q output of said second flipflop, a second input connected to the Q output of said third flipflop, and an output;
- a seventh AND gate having a first input connected to the Q output of said second flipflop, a second input connected to the Q output of said third flipflop, and an output;
- a third OR gate having a first input connected to the output of said sixth AND gate, a second input connected to the output of said seventh AND gate, and an output;
- and
- a switch having a first input connected to the output of said second OR gate, a second input connected to the output of said third OR gate, and an output.
32 more elements
Dependencies are inferred from the claim text.