Frequency synthesizer incorporating digital frequency translator

In a frequency synthesizer for generating an output signal at a first specified frequency with a precision determined by that of an accurate and precise applied clock signal having a second specified frequency higher than said first specified frequency, said first and second specified frequencies bearing no harmonic relationship therebetween;

• said synthesizer comprising:
• first means including a voltage-controlled crystal oscillator, a phase detector coupled to said oscillator for generating a control voltage applied to said oscillator having a value determined by the phase difference between first and second control signals applied as respective inputs to said phase detector, said control voltage applied to said oscillator effecting a reduction in any error between the actual then-existing frequency of said output signal and said first specified frequency;
• second means for producing said first control signal, said second means including a frequency down-converter responsive to the frequency difference between said second specified frequency and the sum of a certain number of derived frequencies harmonically related to the then-existing frequency of said output signal for producing said first control signal, said first control signal having a third specified frequency only when the then-existing frequency of said output signal has exactly said first specified frequency, said third specified frequency being lower than said second specified frequency;
• and
• third means for producing said second control signal, said third means including a digital frequency translator for multiplying the then-existing frequency of said output signal by that preselected certain numerical proper fraction which produces a product frequeny for said second control signal having a value equal to said third specified frequency only when the then-existing frequency of said output signal has exactly said first specified frequency;
• wherein said digital frequency translator includes an ordinal series of a predetermined number of pulse snatchers each having its own associated preselected-integer frequency divider individually interconnected thereto, each pulse snatcher and its frequency divider being responsive to a serial stream of successive pulses applied as an input thereto for removing from said serial stream forwarded to the output of that pulse snatcher one pulse for each count of successive input pulses equal in number to the value of the preselected integer associated with that frequency divider, coupling means for applying as an input to the first of said ordinal series of pulse snatchers a serial stream of pulses derived from and in time synchronous relationship with the frequency of the output signal of said synthesizer and for applying as an input to each other pulse snatcher of said ordinal series the output of the pulse snatcher immediately preceding that other pulse snatcher, and an additional preselected-integer frequency divider having the output of the last pulse snatcher in said ordinal series applied as an input thereto, said respective values of said preselected integers of said frequency dividers being chosen to produce said product frequency for said second control signal at the output of said additional frequency divider.