Master-slave flip-flop circuits
AssigneeLucas Industries Limited
InventorKenneth W. Lambert
Life of this patent
Estimating the term…
Abstract
A d.c. triggered master-slave flip-flop circuit including a master flip-flop with a capacitive delay means at its input, and a slave flip-flop having its input connected to the output of the master flip-flop. A capacitive delay means is connected at the input of the slave flip-flop. The slave flip-flop controls the connections at the input of the master flip-flop in known manner. The two capacitive delay means, serve to make each flip-flop circuit immune to noise pulses and also eliminate multiple triggering caused by contact bounce when the circuit is controlled by mechanical contacts.
Claims2
A d.c.-triggered master-slave flip-flop circuit for operation in conjunction with a signal source, said circuit comprising:
- a master flip-flop circuit having an input and an output, the voltage at said input determining the state of the master flip-flop circuit;
- means providing positive feedback from the output to the input of the master flip-flop circuit;
- slave circuit means, having an input and an output, for alternatively connecting said signal source and said output of said slave circuit means to said master flip-flop circuit input;
- means connecting said input of said slave circuit means to said output of said master flip-flop circuit;
- capacitive delay means, connected to the input of each of the master flip-flop circuit and the slave circuit means, for rendering the master flip-flop circuit and the slave circuit means immune to noise pulses and unintended multiple triggering;
- wherein each of the master flip-flop circuit and the slave circuit means includes a d.c. input and incorporates current source means controllable by the d.c. input to charge and discharge the associated capacitive delay means;
- and
- comparator means connected to compare the voltage on said capacitive delay means with a reference voltage.
Dependencies are inferred from the claim text.