Phase-encoded data signal demodulator

A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising:

• signal source means for generating a reference clock signal;
• digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal;
• means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states;
• means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal;
• means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and second half of each clock cycle interval, and
• means for providing a decoded data signal having a first state for each clock cycle interval where the magnitudes of the totalized counts for the first half and second half of a clock cycle interval is at least as great as a first and second predetermined threshold magnitude, respectively, and having a second state for each clock cycle interval where the magnitudes of the totalized counts for at least one of the first half and second half of a clock cycle interval is less than the first and second predetermined threshold magnitudes, respectively.

A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising:

• signal source means for generating a reference clock signal;
• digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal;
• means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states;
• means for sampling the state of the multiplying means output signal N times during the first and second half of each clock cycle interval to provide successive samples of the multiplying means output signal, where N is an integer number greater than two (2);
• means for counting for each bit interval the samples of the multiplying means output signal having the first state and providing a totalized count for the first half and the combined first and second halves of each clock interval;
• and
• means for providing a decoded data signal having a first state for each clock interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is greater than N and where the totalized count for the combined first and second halves of a clock cycle interval is N and the totalized count for the first half of the clock cycle interval is less than one-half N, and having a second state for each clock cycle interval where the magnitude of the totalized count for the combined first and second halves of a clock cycle interval is less than and where the totalized count for the first and second halves of a clock cycle interval is equal to N and the totalized count for the first half of the clock cycle interval is greater than one-half N.

A demodulator for a phase-encoded data signal transmitted by a signal source at a predetermined bit frequency, comprising:

• signal source means for providing a reference clock signal;
• digital phase-locked loop means responsive to the reference clock signal for generating a data clock signal, having successive clock cycle intervals at the predetermined bit frequency, and phase-locking the generated data clock signal to the phase reversals of the phase-encoded data signal;
• means for multiplying the phase-encoded data signal and the data clock signal to provide an output signal having first and second states;
• means for sampling the state of the multiplying means output signal a predetermined number of times during each clock cycle interval to provide successive samples of the multiplying means output signal;
• means for storing a predetermined weighting factor associated with each sample taken during successively clock cycle intervals;
• means responsive to each sample of the multiplying means output signal having the first state for reading out from the storing means the corresponding predetermined weighting factor;
• means for totalizing the read-out predetermined weighting factors;
• and
• means for providing a decoded data signal having a first state for each clock cycle interval where the magnitude of the totalized weighting factors is at least as great as a predetermined threshold magnitude, and providing a second state for each clock cycle interval where the magnitude of the totalized weighting factors is less than the predetermined threshold magnitude.