Method and circuit arrangement for clock synchronization in the transmission of digital information signals
AssigneeSiemens Aktiengesellschaft
InventorJosef Zemanek
Life of this patent
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Abstract
A method and a circuit arrangement for clock synchronization in the transmission of digital information signals. In the four-wire type transmission of blocks of information signals on a two-wire transmission line it is determined, by phase comparison, whether the first bit in each block of signals (1) falls within a time interval derived from the bit clock signal of the local clock generator; (2) falls within an adjacent time interval or (3) falls within none of such time intervals. Depending upon the results of this comparison, the time relationships are left unchanged, the period of the clock generator is shortened or lengthened one or more times, or a one-time, initial phase equality is established.
Claims5
A method for clock synchronization in the transmission of digital message signals on a two-wire transmission line between a superordinate system, such as a PCM multi-multiplex exchange, and a subordinate system, such as a digital subscriber station, in the form of message signal blocks which comprise at least one message signal word and a prefixed synchronization word, each of said systems having a clock generator for producing a bit clock signal that determines the time relationships within the respective system, the two clock generators of the superordinate and subordinate systems operating plesiochronously to each other, said method comprising the steps at said subordinate system of:
- (a) deriving a periodically repeating time group comprising an odd number of directly succeeding time intervals from the bit clock signal of said subordinate system, the time interval occurring at the center of said time group coinciding with a pulse edge of said bit clock signal;
- (b) repeatedly deriving a receive pulse from the pulse edge of the first bit of said synchronization words in said message signal blocks received at said subordinate system;
- (c) repeatedly determining by phase comparison whether the current receive pulse coincides with one of said time intervals;
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- (d) (1) if a prescribed number of successive receive pulses fail to coincide with any of said time intervals, establishing an initial phase equality between said bit clock signal of said subordinate system and said receive pulses;
- (d) (2) if a receive pulse coincides with the middle time interval of a time group, leaving the phase of said bit clock signal unchanged;
- (d) (3) if a receive pulse coincides with the time interval directly preceding said middle time interval of a time group, shortening the pulse period of said bit clock signal once, and if the next following receive pulse also coincides with the time interval directly preceding said middle time interval of the next following time group, shortening the pulse period of said bit clock signal twice within a transmission period;
- (d) (4) if a receive pulse coincides with the time interval directly following said middle time interval of a time group, lengthening the pulse period of said bit clock signal once, and if the next following receive pulse also coincides with the time interval directly following said middle time interval of the next following time group, lengthening the pulse period of said bit clock signal twice within a transmission period;
- (d) (5) if a receive pulse coincides with one of the time intervals indirectly preceding said middle time interval of a time group, shortening the pulse period of said bit clock signal at least three times within a transmission period upon the first detection of such phase relationship, said number of times depending upon which one of said time intervals said receive pulse coincides with;
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- (d) (6) if a receive pulse coincides with one of the time intervals indirectly following said middle time intervals indirectly following said middle time interval of a time group, lengthening the pulse period of said bit clock signal at least three times within a transmission period upon the first detection of such phase relationship, said number of times depending upon which one of said time intervals said receive pulse coincides with.
A circuit arrangement for clock synchronization in the transmission of digital message signals on a two-wire transmission line between a superordinate system, such as a PCM time-multiplex exchange, and a subordinate system, such as a digital subscriber station, in the form of message signal blocks which comprise at least one message signal word and a prefixed synchronization word, each of said systems having a clock generator for producing a bit clock signal that determines the time relationships within the respective system, the two clock generators of the superordinate and subordinate systems operating plesiochronously to each other, said circuit arrangement being disposed in said subordinate system and comprising, in combination:
- (a) means for deriving a periodically repeating group of time pulses representing an odd number of directly succeeding time intervals from the bit clock signal of said subordinate system, the time interval occurring at the center of said time group coinciding with a pulse edge of said bit clock signal;
- (b) means for repeatedly deriving a receive pulse from the pulse edge of the first bit of said synchronization words in said message signal blocks received at said subordinate system;
- (c) means for repeatedly determining by phase comparison whether the current receive pulse coincides with one of said time intervals;
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- (d) evaluating logic means responsive to said phase comparison means for:
- (1) if a prescribed number of successive receive pulses fail to coincide with any of said time intervals, establishing an initial phase equality between said bit clock signal of said subordinate system and said receive pulses;
- (2) if a receive pulse coincides with the middle time interval of a time group, leaving the phase of said bit clock signal unchanged;
- (3) if a receive pulse coincides with the time interval directly preceding said middle time interval of a time group, shortening the pulse period of said bit clock signal once, and if the next following receive pulse also coincides with the time interval directly preceding said middle time interval of the next following time group, shortening the pulse period of said bit clock signal twice within a transmission period;
- (4) if a receive pulse coincides with the time interval directly following said middle time interval of a time group, lengthening the pulse period of said bit clock signal once, and if the next following receive pulse also coincides with the time interval directly following said middle time interval of the next following time group, lengthening the pulse period of said bit clock signal twice within a transmission period;
- (5) if a receive pulse coincides with one of the time intervals indirectly preceding said middle time interval of a time group, shortening the pulse period of said bit clock signal at least three times within a transmission period upon the first detection of such phase relationship, said number of times depending upon which one of said time intervals said receive pulse coincides with;
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- (6) if a receive pulse coincides with one of the time intervals indirectly following said middle time interval of a time group, lengthening the pulse period of said bit clock signal at least three times within a transmission period upon the first detection of such phase relationship, said number of times depending upon which one of said time intervals said receive pulse coincides with.
Dependencies are inferred from the claim text.