Electronic timepiece

An electronic timepiece comprising:

• a frequency supply for providing a relatively high frequency timebase signal;
• timekeeping circuit means including a frequency converter responsive to said timebase signal for providing a relatively low frequency time unit signal, and timekeeping register means responsive to said time unit signal for providing a plurality of time information signals;
• input means including externally actuatable control means for providing an actuation signal when actuated, and circuit means for producing an input signal in response to said actuation signal;
• first memory circuit means responsive to an initiation of said input signal for being reset to a condition in which output of a signal therefrom is inhibited;
• second memory circuit means responsive to said input signal and to a first one of said time information signals for producing an output signal after a first predetermined time interval following an initiation of said input signal;
• said first memory circuit being responsive to said output signal from the second memory circuit means for being set to produce an output signal;
• circuit means responsive to said input signal and a second one of said time information signals for producing a time delay output signal after a second predetermined time interval following an initiation of said input signal, said second predetermined time interval being of longer duration than said first predetermined time interval;
• gate circuit means responsive to said time delay output signal in conjunction with said output signal from the first memory means for producing an enabling signal;
• and
• control circuit means responsive to said enabling signal for controlling said timekeeping circuit means to correct the timing of said time information signals;
• whereby an actuation of said externally actuatable control means will result in an enabling signal being produced by said gate circuit means following said second predetermined time interval after initiation of said actuation, but whereby a second actuation of said externally actuatable control means before the termination of said second predetermined time interval will cause said first memory circuit means to be reset, thereby cancelling the generation of said enabling signal.