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US 4,302,819 AGranted
Fault tolerant monolithic multiplier
AssigneeHewlett-Packard Company
InventorFrederick A. Ware
Life of this patent
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Abstract
A fault tolerant multiplier which utilizes a plurality of full adder rows has the ability to permanently deselect a row when a fault is detected in its initial testing. An extra row is provided to allow this deselection and transfer gates are provided between each row to shift the sum and carry logic on to the next row at the point of the deselected row and all rows therebeyond.
Claims3
Apparatus for multiplying first and second binary operands each having a nominal length of N bits, said first operand represented by first input signals and said second operand represented by second input signals, said apparatus comprising:
- an array of adder cells comprising means for providing carry and sum logic signals in response to said first and second binary operands, said array comprising a plurality of said adder cells logically arranged in N columns and at least N+ one rows, said array including product means for providing product output signals at the logical end of each row;
- selection logic means coupled to said array of adder cells for selecting N of said N+1 rows by deselecting one of said rows in response to a deselection signal;
- and
- input gating means coupled to said selection logic means for gating in successive order, said ones of said first input signals of said first operand corresponding to said deselected row and the logically succeeding rows to the rows following the deselected one of said N+1 rows.
1 more element
Dependencies are inferred from the claim text.