DC Voltage multiplier using phase-sequenced CMOS switches
AssigneeBurroughs Corporation
InventorClifford J. Bader
Life of this patent
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Abstract
An electronic circuit is described for providing a low current DC supply at increased voltage with high efficiency and minimal hardware complexity. In performing its function, the circuit preferably utilizes a plurality of CMOS voltage-controlled solid state switches in conjunction with a sequenced clock pulse train to implement a compact capacitive-type multiplier. Thus, capacitors are charged in a predetermined order and the charges stacked upon one another to ultimately charge an output storage capacitor to a voltage level which is substantially a desired multiple of the supply voltage applied to the circuit. For descriptive purposes, the present inventive techniques are applied herein to the design for an octupler.
Claims12
A DC voltage multiplier for increasing an input supply voltage to a desired output level comprising:
- a plurality of stages required to produce said desired output level, each of said stages having a pair of switching means with complementary electrical characteristics and being coupled to each other at a common junction,
- a first stage having its pair of switching means coupled between said input supply voltage and a reference potential,
- a capacitor having a first and a second terminal, means coupling said first terminal to said common junction of said pair of switching means,
- unidirectional current conducting means coupling said second terminal of said capacitor to said input supply voltage,
- means for applying multi-phase sequential control signals having first and second predetermined amplitudes in common to the respective pairs of switching means of said plurality of stages, a signal of said first predetermined amplitude being applied sequentially to said stages such that in any given phase, said last mentioned signal is applied to the switching means of one of said stages while signals of said predetermined amplitude are applied respectively to the switching means of all the remaining stages,
- first phase control signals including said signal of said first predetermined amplitude, said last mentioned signal being applied to said switching means of said first stage and causing a first of said pair of the last mentioned switching means connected between said input supply voltage and said common junction to assume a high resistance state and the second of said pair of switching means connected between said common junction and said reference potential to assume a lower resistance state, thereby establishing a charging path for said capacitor and causing the latter to be charged substantially to the level of said input supply voltage,
- second phase control signals including a signal of said second predetermined amplitude, said last mentioned signal being applied to said switching means of said first stage and causing said first of said pair of switching means to assume a low resistance state and said second of said pair of switching means to assume a high resistance state, whereby the charge on said capacitor is stacked upon the level of said input supply voltage such that a potential substantially equal to twice that of the last mentioned voltage appears at said second terminal of said capacitor,
- at least a second stage having a second pair of switching means coupled between said second terminal of said capacitor and said reference potential,
- a second capacitor having a first and a second terminal, means coupling said first terminal of said second capacitor to said common junction of said second pair of switching means,
- a second unidirectional current conducting means coupling said second terminal of said capacitor to said second terminal of said second capacitor.
Dependencies are inferred from the claim text.