Delay line compensation network
AssigneeHoneywell Information Systems Inc.
InventorsChester M. Nibby, Jr., Robert B. Johnson
Life of this patent
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Abstract
A timing generator circuit includes a pair of multitap cascaded delay lines of like construction. Each delay line includes a plurality of sections each of which are constructed to provide the same increment of delay at each tap. A capacitive element connects between predetermined taps of the two delay lines to form a compensation network including a predetermined section of each delay line. The compensation network which operates to cancel out the effects of any mismatch resulting from connecting the delay lines in series.
Claims20
A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising:
- a first multisection delay line having an input terminal for receiving said input timing pulses, a plurality of taps and an output tap;
- a second multisection delay line having an input terminal directly coupled to said output tap of said first delay line and a plurality of taps and an output tap;
- and,
- capacitive means having first and second terminals for connecting said capacitive means between predetermined taps connected to last and first sections of said first and second multisection delay lines forming a compensating network with the corresponding sections of said delay lines for cancelling voltage reflections produced by connecting said first and second delay lines in series.
A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising:
- a first delay line having a plurality of like constructed sections, an input terminal for receiving said input timing pulses, a plurality of taps and an output tap;
- a second delay line having a plurality of said like constructed sections, an input terminal directly coupled to said first delay line output tap, a plurality of taps and an output tap;
- capacitive means having first and second terminals for connecting said capacitive means between predetermined taps connected to last and first sections of said first and second delay lines forming a compensating network with said last and first sections of said delay lines, said network being operative in response to said input timing pulses to apply voltage signals of sufficient amplitude, correct phase and polarity to cancel with voltage spikes generated by connecting said first and second delay lines in series.
A timing generator circuit for generating a sequence of output timing pulses in response to input timing pulses, said circuit comprising:
- first and second delay lines having a number of sections, and input terminal and a corresponding number of taps and an output tap, said first delay line input terminal being connected to receive said input timing pulses and said first delay line output tap being directly connected to said second delay line input terminal;
- and,
- a compensating network comprising:
- a last one of said number of sections of said first delay line;
- a first one of said number of sections of said second delay line;
- and,
- capacitive means having first and second terminals, said first terminal and second terminals being connected between said first one of said sections of said second delay line and said last one of said sections of said first delay line respectively, said compensating network being operative in response to said input timing pulses to apply voltage signals of predetermined polarities and phase for cancelling voltage reflections produced by connecting said first and second delay lines in series.
Dependencies are inferred from the claim text.