Harmonic phase locked loop with undesired DC component suppression

A phase-locked loop comprising:

• voltage-controlled oscillator means for producing a clock output signal having a frequency in accordance with an applied error control voltage signal,
• phase detector means coupled to said oscillator means for comparing said clock output signal with an incoming data signal and producing a first signal having an average voltage amplitude proportional to the phase difference between the clock output signal and the incoming data signal,
• first amplifying means coupled to said phase detector means for amplifying without inverting said first signal, second amplifying means also coupled to said phase detector means in parallel with said first amplifying means for amplifying and inverting said first signal,
• first filter means coupled to said first amplifying means for producing a first low-frequency signal by extracting the low-frequency components from said non-inverted amplified first signal,
• second filter means coupled to said second amplifying means for producing a second low-frequency signal by extracting the low-frequency components from said inverted, amplified first signal, and
• combining means coupled to said first and second filter means for differentially combining said low-frequency signals to produce said applied error control voltage signal having an amplitude which is substantially equal to the sum of the voltage amplitudes of said first and second low-frequency signals and any undesired D.C. voltage components present in the low-frequency signals have been mutually cancelled out.