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US 4,302,665 AGranted
Circuit for measuring the duration of a pulse train, its use and circuit for its use
AssigneeITT Industries, Inc.
InventorWolfgang Hoenig
Life of this patent
Estimating the term…
Abstract
A circuit is provided for the fading compensation in car radio receivers equipped with the so-called traffic decoder decoding for example the area designating signal. An up-down counter, a memory and a coincidence gate are interconnected to maintain the measured pulse duration over a selectable time period.
Claims3
A circuit for measuring the period of a pulse train comprising:
- means for generating pulses at regular intervals, a predetermined number of said pulses defining a measuring period,
- a counter for deriving a count during said measuring period, said counter having a counting input, a condition input and a reset input,
- a memory for storing the count available at the end of said measuring period,
- an arrangement for indicating the memory contents,
- a coincidence gate for comparing the count of the counter after each measuring period, with the contents of the memory,
- a bidirectional forward-backward counter, having a highest value and a zero position and including a counting input to which one counting pulse is applied per measuring period, wherein said bidirectional counter is switched by the coincidence gate to a forward counting in the event of an equality of both the count and the memory contents, and to backward counting in the event of an unequality, and wherein its counting input is blocked upon reaching its highest value or its zero position when simultaneously switched to forward counting or backward counting by the coincidence gate, and which only in its zero position permits the count to be read into the memory, and a sequence control circuit controlled by said pulse train, said control circuit having an input to which the pulse train is applied and first through fifth outputs, said first output providing a condition signal to said condition input of said counting means, said second output providing a reset signal to said reset input of said counting means, said third output providing a condition signal to said coincidence gate, said fourth output providing a control signal to said memory, and said fifth output providing a pulse signal to an input of said bidirectional counter.
3 more elements
Dependencies are inferred from the claim text.