Decimator apparatus for decreasing the word rate of a digital signal of the type employed in digital telephone systems

A recursive filter structure of the low pass type having a transfer function F(Z) enabling filter coefficients G.sub.1 and G.sub.2 to be of the form 2.sup.-K, where K is an integer, said recursive filter having a transfer function F(Z) equal to:

• ##EQU10## where:
• Z.sup.-1 =one word delay at the input word rate of a digital signal to be filtered
• Z.sup.-2 =a two word delay at the input word rate of a digital signal to be filtered,
• the combination therewith of a first order error correcting circuit in said filter for implementing said coefficients G.sub.1 and G.sub.2 of the form 2.sup.-K, comprising:
• summing means for receiving at one input thereof a digital signal of a given number of desired bits, indicative of a first digital word to be filtered, and a second input thereof for providing an error signal to provide at an output of said summing means, a new word of said desired number of bits modified by said error signal,
• register means adapted to receive at an input thereof said new word and being responsive to the receipt of said new word to shift said new word a given number of bit positions indicative of a division by 2.sup.K, for providing a divided output word having a reduced number of bits equivalent to the N most significant bits, and means for storing the K least significant bits not employed in said output word for applying said K bits as an error signal to said second input of said summing means to be added to said next digital word, whereby each successive digital word as modified by said filter means provides a first order reduction in noise operation of said recursive filter as determined by said error signal.

In a recursive filter structure of the low pass type having a transfer function F(Z) enabling filter coefficients G.sub.1 and G.sub.2 to be of the form 2.sup.-K, where K is an integer, said recursive filter having said transfer function F(Z) equal to:

• ##EQU11## where:
• Z.sup.-1 =one word delay at the input word rate fs of a digital signal to be filtered
• Z.sup.-2 =a two word delay at said word rate fs,
• the combination therewith of a second order correcting circuit for implementing said coefficients G.sub.1 and G.sub.2 of the form 2.sup.-K, comprising:
• summing means having first, second and third inputs, means for applying at said first input a digital signal of a given number of desired bits, indicative of a first word to be filtered, for providing at an output, a new word of said desired number of bits modified by first and second error signals applied to said second and third inputs,
• first register means adapted to receive said new word and responsive to the receipt of said new word to shift the same a given number of places indicative of a division by 2.sup.K for providing a divided output word at a reduced number of bits N equivalent to the N most significant bits, and means for storing the K least significant bits not employed in said output word,
• logic means for storing said K least significant bits including means for shifting said K bits one place to the left to multiply the same by a factor of two, for applying said multiplied K bits to said second input of said summing means to modify the next word received at said input, and means for applying said K bits as stored to said third input of said summing means for modifying the word after said next word as received at said first input, wherein all words received at said first input will be modified by both said K bits and said multiplied K bits to provide a second order error reduction in noise operation of said recursive filter as determined by both said K bits and said multiplied K bits.

A method of implementing the coefficients G.sub.1 and G.sub.2 as present in a recursive filter structure having a transfer function F(Z) equal to:

• ##EQU12## where:
• Z.sup.-1 =one word delay at the input word rate fs of a digital signal to be filtered
• Z.sup.-2 =a two word delay at said rate fs comprising the steps of:
• selecting G.sub.1 and G.sub.2 to be of the form 2.sup.-K where K is an integer,
• dividing a digital signal processed by inserting said signal in a register, shifting said contents K places to the right to perform a division by 2.sup.K, to provide a divided digital signal, having a given number of bits, N+K,
• truncating said divided signal into a given number of most significant bits N, to provide a signal indicative of a coefficient as G.sub.1 or G.sub.2,
• storing said K least significant bits,
• adding said K bits as stored to the next digital signal received by said dividing means to provide an error corrected signal for said dividing means operative to reduce inband noise of a first order.

A telephone subscriber line circuit for coupling a subscriber to a digital transmission path in a telephone switching system, comprising in combination:

• two-to-four wire converter means coupled to a near-end subscriber line to provide a transmit path and a receive path for said line,
• an analog to digital converter means for sampling low-rate near-end analog signals to generate a high rate pulse stream of 1-bit digital words representative of said near end analog signals,
• decimator means for transforming groups of said high rate 1-bit digital words into corresponding multiple-bit digital words and for discarding a predetermined number of multiple bit words in sequential sets to provide a decimated output signal at a decreased word rate, said decimator comprising:
• a cascaded digital filter arrangement having an input and an output terminal, with a finite impulse response filter (FIR) in cascade with and coupled to the input of a second order digital low pass recursive filter characterized in having a transfer function defining filter coefficients to be of the form 2.sup.-K, where K is an integer, to permit filtering of said digital signal from said analog to digital converter as applied to said input terminal of said cascaded arrangement, to provide at said output terminal, an output filtered digital signal having a plurality of words, each of said greater number of bits and at said high word rate,
• register means responsive to said filtered output signal from said recursive filter of said greater number of bit words for transferring said output signal at a lower rate than said predetermined rate, whereby said register means provides at an output, a decimated signal having a decreased word rate, each of said words having a greater bit length and manifesting the weighted value of said input words from said analog to digital converter;
• means for applying said decimated digital signal to said digital transmission path,
• means coupled to said digital transmission path adapted to receive a far end digital signal of the same format as said applied decimated digital signal,
• interpolator means responsive to said decimated digital signal as received for providing a second digital signal having a lesser number of bits than said far digital signal and an increased word rate,
• digital to analog converter means in said receive path of said line circuit and coupled to the output of said interpolator means and responsive to said second digital signal to
• provide an analog signal at its output,
• said output from said interpolator manifesting said far end analog signal,
• means for coupling said far end analog signal to said two-to-four wire converter means to enable a subscriber to receive and therefore respond to said far end analog signals.