Sensing technique for memories with small cells

Abstract

A sensing technique or system is provided for a merged charge memory having similar storage and dummy cells with the dummy cells being charged with a reference voltage equal to 1/2 of the sum of the voltages representing 1 and 0 binary digits of information in the memory. The sensing technique or system includes an insulating layer disposed on a semiconductor substrate, a memory array having a data word line coupled to a first plurality of spaced apart conductive films formed on the insulating layer defining a plurality of data storage capacitors, sensing means having first and second terminals and a dummy line coupled to a second plurality of spaced apart conductive films formed on the insulating layer defining a plurality of reference voltage capacitors. Charge source means are coupled to the first plurality of conductive films by the word line and to the second plurality of conductive films by the dummy line. The first terminal of the sensing means is coupled to a conductive film of the first plurality of films spaced a predetermined distance from the charge source means and the second terminal of the sensing means is coupled to a given conductive film of the second plurality of films spaced the predetermined distance from the charge source means. The reference voltage is derived from the first and second terminals of the sensing means and applied to the given conductive film.

Dependencies are inferred from the claim text.