A microprocessor system which cooperates with an application-dependent logic module to form a universal-type peripheral-controller capable of handling data transfers between a host computer and a plurality of peripheral terminal units which can be either "word-oriented" or "byte-oriented", and wherein said application-dependent logic module provides external register means having bus connections to said plurality of peripheral terminal units and to said host computer, and wherein said application-dependent logic means further includes an external memory for storage of programs related to control of said peripheral terminal units and for storage of data undergoing transfer, and wherein said application-dependent logic module further includes control logic means for communicating with and controlling said external register means, said external memory and said microprocessor system, the said microprocessor system comprising:
- (a) data processing means including:
- (a1) an Arithmetic Logic Unit providing an output to a shift logic circuit and to a byte-swap circuit;
- (a2) said shift logic circuit providing output to an I/O bus, said shift logic circuit functioning to rotate one or more bits of a word being processed to the right or to the left;
- (a3) said byte swap circuit providing output to said I/O bus, said byte swap circuit functioning to exchange the sequential positions of the higher order byte and the lower order byte of a received two-byte word;
- (b) said I/O bus providing connecting lines from said data processing means to said external registers, to said external memory, to an accumulator register means, and to an addressing means;
- (c) addressing means receiving input data from said I/O bus and storing addresses useful for accessing data from an internal memory or said external memory, said addressing means including:
- (c1) a program counter connected to said I/O bus for storing consecutive addresses of data in said internal program memory;
- (c2) a memory reference register connected to said I/O bus for storing addresses of data in said external memory, and including:
- (c2-1) a memory address bus which connects to said external memory;
- (c2-2) and wherein a dedicated non-address bit (byte-select bit) in said memory reference register being set to signal a decoder-controller to initiate a byte-swap operation in said byte-swap circuit, or when not-set, to pass data without a byte-swap operation;
- (c2-3) a bus connection from said memory reference register to said decoder-controller;
- (d) said internal program memory storage for storing program instructions and data words, said internal memory being addressed from said program counter and providing instruction words and data, via an instruction bus, to an instruction register and memory operand register;
- (e) register means for temporary storage of data, said register means including:
- (e1) said accumulator register means which includes a plurality of accumulator registers which provide an output to the input of said Arithmetic Logic Unit, said accumulator registers receiving input data words from said I/O bus, said plurality of accumulator registers connected by means of an:
- address bus means from said decoder-controller for addressing selected accumulator registers in said plurality of accumulator registers;
- (e2) said memory operand register for receiving operand data from said internal program memory storage via said instruction bus or from said external memory via a memory data bus;
- (e3) said instruction register for receiving instruction words from said internal program memory storage via said instruction bus and providing said instruction words to said decoder-controller;
- (f) said instruction decoder-controller receiving instruction signals from said instruction register, and including incoming and outgoing control signal lines connected to said data processing means, to said addressing means, to said register means, to said internal and external memory means, to said external registers and said control logic means;
- (g) and wherein said register means, said internal program memory storage, and said external memory are organized into word locations of 16-bits and each word is symbolically designated as AB to indicate the two 8-bit bytes;
- (h) and wherein said microprocessor system includes means whereby during the byte-oriented operation, which will access the lower order byte only placed on said I/O bus;
- (i) and wherein said byte-swap circuit includes means to position a desired byte of data, which is located in the higher order position A of AB, into the lower order position, as BA, to make it available for handling as a single byte of data, said position-swapping of byte-data locations occurring only when said dedicated non-address bit in said memory reference register is SET;
- (j) said memory data bus for carrying data from said external memory to said instruction register and said memory operand register.