Quadriphase differential demodulator
AssigneeNCR Corporation
InventorsAugustinus M. Jansen, Arien Groot
Life of this patent
Estimating the term…
Abstract
A method and apparatus for synchronizing a digital data demodulator to a received phase modulation carrier signal in which the carrier signal is phase shifted during each modulation period of the carrier to represent one of four pairs of binary bits or dibits. A dibit clock is adjusted to the phase of a reference dibit clock whose output is used to synchronize the demodulator in establishing the location of the modulation period of the incoming carrier. In order to overcome errors found in the decoding of the carrier signal, the adjustment of the dibit clock is suppressed when the dibits 00 and 10 are being decoded.
Claims17
In a differentially encoded phase-modulated data transmission system in which a carrier signal is phase shifted over a data interval at a modulation rate to represent one of a plurality of pairs of data bits for transmission to a receiver, a demodulator apparatus for decoding the transmitted pairs of data bits comprising:
- means for detecting the start of each data interval in the received carrier signal;
- means for generating first clock pulses in response to the detecting of said data intervals;
- means for generating second clock pulses in response to the generation of said first clock pulses;
- means for decoding the carrier signal to derive a first control signal representing a predetermined pair of data bits transmitted in response to receiving said second clock pulses;
- means for adjusting the phase of the second clock pulses to the phase of the first clock pulses;
- and means responsive to the generation of said first control signal for disabling the operation of said adjusting means.
In a differentially encoded phase-modulation data transmission system in which a carrier signal is phase shifted over a data interval at a modulation rate to represent a pair of data bits for transmission to a receiver, a demodulator apparatus in the receiver for decoding the transmitted data comprising:
- means responsive to receiving said carrier signal for generating a first control signal representing the start of a data interval;
- means for generating a first clock signal operated in response to receiving said first control signal;
- means for generating a second clock signal in response to the generation of said first clock signal;
- means for adjusting the phase of the second clock signals to the phase of the first clock signal;
- demodulator means operated in response to receiving said carrier signal and said second clock signal for generating a second control signal representing a predetermined pair of said data bits, and
- means for disabling said adjusting means in response to the generation of said second control signal wherein the second clock signal will synchronize the operation of said demodulator means with the carrier signal containing the next pair of data bits.
A method for synchronizing the demodulation of a differentially encoded phase-modulated carrier signal in which the carrier signal is phase shifted over a data interval to represent one of a plurality of pairs of data bits comprising the steps of:
- detecting the start of a data interval in the carrier signal;
- generating a first clock pulse representing the data interval upon detecting the start of the data interval;
- generating a second clock pulse representing approximately the data interval;
- adjusting the phase of the second clock pulse to the phase of the first clock pulse;
- demodulating the carrier signal in accordance with the phase of the second clock pulse to generate a first control signal representing a predetermined pair of data bits;
- and disabling the adjusting step upon the generation of said first control signal.
Dependencies are inferred from the claim text.