TTL-Compatible address latch with field effect transistors
AssigneeInternational Business Machines Corporation
InventorsRainer Clemen, Joerg Gschwendtner, Werner Haug
Life of this patent
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Abstract
Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.
Claims6
A field effect transistor circuit, for converting first and second relatively low logic voltage levels to first and second relatively higher logic voltage levels, comprising:
- first and second field effect transistors having drain, source, and gate electrodes, their drain and gate electrodes being respectively cross coupled forming first and second latch nodes, their source electrodes being connected in common;
- first circuit means connected to the first and second latch nodes for precharging the first and second latch nodes to the first relatively higher logic level from a first potential source;
- a third field effect transistor having drain, source, and gate electrodes for selectively isolating the common source connection of said first and second field effect transistors from a second potential source;
- an input terminal for receiving said first and second relatively low logic voltage levels;
- second circuit means for coupling said input terminal to said first latch node;
- a control terminal for receiving a clock pulse signal;
- and
- capacitive means for coupling the control terminal only to the first latch node and not to the second latch node such that the occurrence of a clock pulse at said control terminal causes charge to be coupled only to said first latch node.
Dependencies are inferred from the claim text.