Data processing system having data multiplex control apparatus

A data processing system comprising a main memory capable for storing a plurality of data words, each of said data words being addressed by a unique memory address, a central processing unit (CPU) coupled to said main memory, at least one input/output controller (IOC), said CPU and said at least one IOC coupled to a common bus for the transfer of information between said CPU and said at least one IOC during information transfer cycles, said CPU further comprising:

• A. first means, included in said CPU, for receiving an IOC identification signal via said common bus from a one IOC of said at least one IOC, said IOC identification signal for identifying said one IOC of said at least one IOC desiring to make a transfer of a single unit of data between said one IOC and said main memory, said IOC identification signal being generated by said one IOC in response to an answer request signal;
• B. second means, included in said CPU and coupled to said first means, for receiving data via said common bus from said one IOC and transferring it to said main memory or for receiving data from said main memory and transferring it via said common bus to said one IOC in response to said IOC identification signal;
• C. control means, included in said second means, for controlling the execution of software instructions and said transfer of said single unit of data between said at least one IOC and said main memory;
• D. hardware interrupt means, included in said second means and coupled to said control means, for responding to a transfer request signal from said one IOC by interrupting the execution of software instructions by said control means and causing said control means to send said answer request signal to said one IOC;
• and
• E. grant means, included in said control means and coupled to said common bus, for sending said grant signal via said common bus to said one IOC to indicate that said control means and said common bus are dedicated to said transfer of said single unit of data between said one IOC and said main memory, whereby said control means at any moment is either controlling the execution of software instructions or said transfer of said single unit of data such that said transfer of said single unit of data temporarily suspends the execution of software instructions and whereby, once a transfer of a block of one or more of said single units of data is initiated by a software instruction, each transfer of said single unit of data occurs asynchronously from the execution of any software instruction.