Time compression multiplexing of video signals
AssigneeBell Telephone Laboratories, Incorporated
InventorBarin G. Haskell
Life of this patent
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AssigneeBell Telephone Laboratories, Incorporated
InventorBarin G. Haskell
Estimating the term…
Frequency and time division multiplexing arrangements are common for efficiently utilizing bandwidth in a communication system. Still another, lesser known arrangement is called time compression multiplexing. In time compression multiplexing, a signal from each input channel is stored for a short period of time. The signals from all channels are then read from the store, compressed in time and transmitted over a communication path to a receiver. Unfortunately, the art appears to be remiss in the time compression multiplexing of video signals. The subject signal processor includes a plurality of input terminals (111, . . . , 11N), each input terminal being adapted to receive a video signal, each video signal including a plurality of scan lines, each scan line having a time duration T seconds. The signal processor also includes an arrangement for compressing a video signal by a factor M (illustratively M=N). More specifically, the signal processor compressing arrangement includes apparatus (120, 131, . . . , 13N) for modulating each input video signal with a chirp signal. A first, predetermined delay (142, . . . , 14N) is introduced to the modulated signals, which may be added (150 ). The compressing arrangement also includes apparatus (160) for introducing a second, variable delay to the modulated video signals, e.g., with a dispersive filter (160). The resultant time compressed signal is extracted from the dispersive filter output by an envelope detector (170) and extended over a communication path (300) to a receiver (200) where the time compressed signal is expanded through a receiver modulator (230), distributing apparatus (240), dispersive filter (261, . . . , 26N) and envelope detector (271, . . . , 27N) for extension to a plurality of output terminals (281, . . . , 28N).
A signal processor including a plurality of input terminals (111, . . . , 11N) each input terminal adapted to receive a video signal, said video signal including a plurality of scan lines, a scan line having a predetermined time duration, first means for compressing said video signal, said first compressing means including a plurality of first delay networks (142, . . . , 14N), an adder (150) for adding said compressed signals and means for extending a sum output of said adder to a communication path (300) and CHARACTERIZED IN THAT said signal processor further comprises:
Dependencies are inferred from the claim text.