US 4,299,024 AGranted

Fabrication of complementary bipolar transistors and CMOS devices with poly gates

AssigneeHarris Corporation

InventorLeo R. Piotrowski

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Abstract

Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

Claims16

Dependent claims

In a process for fabricating an integrated circuit in a substrate having high performance, complementary bipolar transistors and complementary insulated gate field effect transistors including base, emitter, source and drain regions, collector, base and body contact regions, gate oxide, gate structure and device contacts the improvement comprising:

depositing N conductivity type impurities through openings in oxide mask layer to form emitter regions of an NPN bipolar transistors and N contact regions as the last device region forming step;
removing portions of said oxide mask layer to expose the channel of said field effect transistors;
forming a gate insulator layer on said substrate;
forming a layer of doped polycrystalline silicon on said gate insulator layer immediately after forming said gate insulator layer;
delineating said polycrystalline silicon layer to define field effect transistor gate structures and first level interconnects;
depositing by chemical vapor deposition a layer of phosphorous doped silicon oxide;
removing portions of said chemically vapor deposed layer to expose portions of said polycrystalline layer and portions of said oxide mask to expose portions of said substrate;
and
depositing and delineating a metallic layer to form second level interconnects and contacts.

6 more elements

A process for simultaneously fabricating high voltage, high performance NPN, PNP and P and N channel MOS devices in dielectrically isolated islands comprising:

introducing P conductivity type impurities into selected N conductivity type substrate regions having an impurity concentration of approximately 1.times.10.sup.15 carriers per cubic centimeter to form a collector region of the PNP and body of an N channel MOS having a surface impurity concentration of approximately 1.times.10.sup.16 carriers per cubic centimeter;
introducing N conductivity type impurities into said P type collector region to form an N type base region and into said P type body to form N type source and drain regions having a surface impurity concentration of approximately 3.times.10.sup.18 carriers per cubic centimeter;
introducing P conductivity type impurities into selected N conductivity type substrate regions to form a base region of the NPN and source and drain regions of a P channel MOS having a surface impurity concentration of approximately 5.times.10.sup.18 carriers per cubic centimeter;
introducing P conductivity type impurities into N conductivity type base regions and selected P conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 2.times.10.sup.20 carriers per cubic centimeter;
introducing N conductivity type impurities into P conductivity type base regions and selected N conductivity type regions to form emitter regions and contact regions respectively having a surface impurity concentration of approximately 1.times.10.sup.21 carriers per cubic centimeter;
and
forming gate oxide and gate electrode structure for the N and P channel MOS devices.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/124,201Filed 25 Feb 1980
Granted: 10 Nov 1981
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 20/40
Interconnections in chips, wafers or substrates: interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or…
H10D 84/0109
Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00,…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/401
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by…