LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same

A readily testable electronic system for providing a useful function, said electronic system comprising:

• a plurality of minimum replaceable units, each of said unit including a shift register segment having at least first, second and third stages, each of said shift register segments having an input, an output and shift control means;
• connection means connecting the at least first, second and third stages of each shift register segment of each said minimum replaceable unit to form a single large shift register having an input, output and shift control means;
• additional controllable means, said additional controllable means being connected to said plurality of minimum replaceable units and including a test combinational circuit for each shift register segment of each minimum replaceable unit, each said test combinational circuit being connected to the shift register segment of the minimum replaceable unit with which it is associated and setting a predetermined bit pattern in only said first two stages of the shift register segment to which it is connected for test purposes;
• and
• pulse source means connected to said additional controllable means and said shift control means of said single large shift register for causing the content of said single large shift register to be shifted out, whereby monitoring the output of said single large shift register a malfunctioning minimum replaceable unit may be identified.

In a readily testable electronic system for performing a useful function, said readily testable electronic system comprising:

• at least first, second, third and fourth minimum replaceable units (2A, 2B, 2C, 2D, FIG. 1), each said minimum replaceable unit including a multi-stage shift register segment having at least first, second and third stages, and each of said minimum replaceable units also including a test combinational circuit connected only to said first and second stages of the shift register segment of its minimum replaceable unit;
• each of said test combinational circuits (5, FIG. 2) of each said minimum replaceable unit comprising, a first INVERTER circuit (20, FIG. 2) having an input connected to a source of test pulses (8, FIG. 2) and an output, a second INVERTER circuit (21, FIG. 2) having an input connected to a source of shift pulses (6, FIG. 2) and an output, a first NAND circuit (23, FIG. 2) having a first input connected to said source of test pulses, a second input and an output, and a second NAND circuit (22, FIG. 2) having a first input connected to said output of said first INVERTER circuit, a second input connected to said output of said second INVERTER circuit and an output;
• each said stage of each said shift register segments of each said minimum replaceable unit including a Master Latch (40, FIG. 2) and a Slave Latch (30, FIG. 2);
• each Master Latch of each of said first shift register stage of each of said shift register segments comprising, a third NAND circuit (24, FIG. 2) having a first input connected to said output of said first NAND circuit of said test combinational circuit, a second input connected to said output of said second NAND circuit of said test combinational circuit, a third input connected to a source of master clock pulses (80, FIG. 2), and an output, a fourth NAND circuit (25, FIG. 2) having at least a first input connected to a source of data inputs (3, FIG. 2) and an additional input connected to a source of system clock pulses (84, FIG. 2), and an output, a fifth NAND circuit (26, FIG. 2) having a first input connected to a source of inverted master clock pulses (81, FIG. 2), a second input connected to a source of inverted system clock pulses (85, FIG. 2), a third input and an output, and a sixth NAND circuit (27, FIG. 2) having a first input connected to said output of said third NAND circuit, a second input connected to a said output of said fourth NAND circuit, a third input connected to said output of said fifth NAND circuit and an output connected to said third input of said fifth NAND circuit, said output of said sixth NAND circuit also providing the output of said Master Latch (45, 4, FIG. 2);
• each slave latch of each of said first shift register stage of each of said shift register segments comprising, a seventh NAND circuit (28, FIG. 2) having a first input connected to the output (of said sixth NAND circuits) of its associated Master Latch, a second input connected to a source of slave clock pulses (82, FIG. 2) and an output, an eighth NAND circuit (29, FIG. 2) having a first input connected to a source of inverted slave clock pulses (83, FIG. 2), a second input and an output, and a ninth NAND circuit (30, FIG. 2) having a first input connected to said output of said seventh NAND circuit, a second input connected to said output of said eighth NAND circuit and an output connected to said second input of said eighth NAND circuit, said output of said ninth NAND circuit also providing the output (48, 4 FIG. 2) of said Slave Latch, said output of said slave latch is connected (181, FIG. 2) to said first input of said first NAND circuit of said test combinational circuit;
• each master latch of each of said shift register stages, other than said first stage, of each of said shift register segment comprising, a tenth NAND circuit (24, FIG. 2) having an input connected to the output of the slave latch of its preceding shift register stage, a second input connected to said source of master clock pulses (80, FIG. 2) and an output, an eleventh NAND circuit (25, FIG. 2) having at least a first input connected to said source of data inputs (3, FIG. 2) and an additional input connected to said source of system clock pulses (84, FIG. 2) and an output, a twelfth NAND circuit (26, FIG. 2) having a first input connected to said source of inverted master clock pulses (81, FIG. 2), a second input connected to said source of inverted system clock pulses (85, FIG. 2) a third input and an output, a thirteenth NAND circuit (27, FIG. 2) having a first input connected to said output of said tenth NAND circuit, a second input connected to said output of said eleventh NAND circuit, a third input connected to said output of said twelfth NAND circuit and an output connected to said third input of said twelfth NAND circuit, said output of said thirteenth NAND circuit also providing the output (45, 4, FIG. 2) for said master latch;
• and
• each slave latch of each of said shift register stages, other than said first stage, of each of said shift register segments, comprising a fourteenth NAND circuit (28, FIG. 2) having a first input connected to said output (of said thirteenth NAND circuit) of its associated Master Latch, a second input connected to said source of slave clock pulses (82, FIG. 2), and an output, a fifteenth NAND circuit (29, FIG. 2) having a first input connected to said source of inverted slave clock pulses (83, FIG. 2), a second input and an output, a sixteenth NAND circuit (30, FIG. 2) having a first input connected to the output of said fourteenth NAND circuit, a second input connected to the output of said fifteenth NAND circuit and an output connected to the second input of said fifteenth NAND circuit, said output of said sixteenth NAND circuit also providing the output (48, 4, FIG. 2) for said slave latch.