Parity prediction circuitry for a multifunction register
AssigneeNCR Corporation
InventorRolfe D. Armstrong
Life of this patent
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AssigneeNCR Corporation
InventorRolfe D. Armstrong
Estimating the term…
Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.
In a data processing system, the combination of:
Circuitry for predicting parity for a multifunction register having control inputs for receiving control signals that select the function of said register, said circuitry comprising:
In a data processing system having a register for performing any selected one of a plurality of functions such as COUNT, SHIFT, LOAD, and COMPLEMENT, prediction circuitry for predicting the parity for the data stored in said register, comprising:
In a data processing system having a register for storing data and operating as a binary counter and having prediction circuitry for predicting the parity of the next count of the register, the improvement wherein said prediction circuitry comprises:
Dependencies are inferred from the claim text.