Active refresh circuit for dynamic MOS circuits

Circuitry for active refreshing of digit lines in a MOS dynamic random access memory comprising:

• a first transistor having a channel connected between a source of a drain supply voltage and a digit line, and a gate;
• a second transistor having a source connected to said first transistor gate, a drain, and a gate;
• a third transistor having a source connected to said digit line, a drain connected to said second transistor gate, and a gate;
• and
• control means for sequentially:
• precharging said second transistor gate to a first potential near said drain supply voltage;
• applying a reference potential to said third transistor gate after the state of a memory cell connected to said digit line has been read by a sense amplifier, said first reference potential being less than a digit line precharge voltage plus one threshold and applying a second potential near said drain supply voltage to the drain of said second transistor.

A method of selectively refreshing a capacitive node to a high logic state as a function of a preestablished voltage level on that node comprising:

• precharging the gate of a first transistor to a first potential near a drain supply voltage;
• applying a reference potential no greater than one threshold above a minimum voltage representing a high logic state to the gate of a second transistor having a channel connected between the gate of said first transistor and said first node to selectively discharge said first transistor gate as a function of node potential;
• applying a second potential near said drain supply voltage to the drain of said first transistor;
• and
• connecting the source of said second transistor to the gate of a third transistor connected between a source of said drain supply voltage and said node.

A method of actively refreshing a digit line in a MOSFET dynamic random access memory comprising:

• precharging the gate of a first transistor to a first potential near a drain supply voltage;
• after the state of a memory cell connected to said digit line has been sensed by a dynamic sense amplifier, applying a reference potential, less than a digit line precharge voltage plus one threshold, to the gate of a second transistor connected between the gate of said first transistor and said digit line to selectively discharge said first transistor gate as a function of digit line potential;
• applying a second potential near said drain to the drain of said first transistor;
• connecting the source of said second transistor to the gate of a third transistor connected between a source of said drain potential and said digit line.