Microprocessor system with specialized instruction format

A universal-type microprocessor system which cooperates with an application-dependent logic module to form a peripheral-controller capable of handling data transfers between main memory of a host computer and a plurality of peripheral terminal units which can be either "word-oriented" or "byte-oriented", and wherein said application-dependent logic module provides external register means having bus connections to said plurality of peripheral terminal units and to said host computer, and wherein said application-dependent logic module further includes an external memory for storage of programs related to control of said peripheral terminal units and for temporary storage of data undergoing transfer, and wherein said application-dependent logic module further includes control logic means for communicating with and controlling said external register means, said external memory and communicating with a decoder-controller in said microprocessor system, the said microprocessor system comprising:

• (a) data processing means including:
• (a1) an Arithmetic Logic Unit providing an output to a shift logic circuit and to a byte-swap circuit;
• (a2) said shift logic circuit providing output to an I/O bus, said shift logic circuit functioning to rotate one or more bits of a word being processed to the right or to the left;
• (a3) said byte-swap circuit providing output to said I/O bus, said byte-swap circuit functioning to exchange the sequential positions of the higher order byte and the lower order byte of a received two-byte word;
• (b) said I/O bus providing connection lines from said data processing means to said external register, to said external memory, to an accumulator register means, and to an addressing means;
• (c) addressing means receiving input data from said I/O bus and storing addresses useful for accessing data from an internal memory or said external memory, said addressing means including:
• (c1) a program counter storing consecutive addresses of data located in said internal program memory;
• (c2) a memory reference register connected to said decoder-controller for storing addresses of data located in said external memory, and including:
• (c2-1) a memory address bus which connects to the said external memory;
• (c2-2) and wherein a dedicated non-address bit (byte-select bit) in said memory reference register being set to signal said decoder-controller to initiate a byte-swap operation in said byte-swap circuit, or when not-set, to pass data without a byte-swap operation;
• (c2-3) a bus connection from said memory reference register to said decoder-controller;
• (c3) an address register in said decoder-controller connecting by means of an address bus to said accumulator register means, which include a plurality of accumulator registers, for selection of an addressed accumulator register as a destination for data or as a source of data;
• (d) said internal program memory for storing program instructions and data words, said internal memory being addressed from said program counter and providing instruction words and data, via an instruction bus, to an instruction register and memory operand register;
• (e) register means for temporary storage of data, said register means including;
• (e1) said plurality of addressable accumulator registers which provide an output to the input of said Arithmetic Logic Unit, said accumulator registers receiving input data words from said I/O bus;
• (e2) a memory operand register for receiving operand data from said internal program memory via an instruction bus or from said external memory via a memory data bus;
• (e3) an instruction register for receiving instruction words from said internal program memory via said instruction bus and providing instruction words to said decoder-controller;
• (f) said instruction decoder-controller receiving instruction signals from said instruction register, and including incoming and outgoing control signal lines connected to said data processing means, to said addressing means, to said register means, to said internal and external memory means, to said external registers and said control logic means, said instruction decoder-controller further including:
• (i) circuitry responsive to each data field of an instruction word for executing the requirements of each of said data field;
• (g) said external memory data bus for carrying data from said external memory to said instruction register and said memory operand register;
• (h) an instruction word format in said internal program memory which includes:
• (h1) a basic function instruction field for initiating transfer of the contents of a selected register to another selected register or for selecting an Arithmetic Logic Unit operator or a program stack operator;
• (h2) a variant function field for initiating selection of:
• (i) an addressed external register for a GET operation or a PUT operation;
• (ii) an Arithmetic Logic Unit OP code or
• (iii) a condition test or program stack operator;
• (h3) a destination field for:
• (i) placement of data resulting from GET and Arithmetic Logic Unit operators;
• (ii) placement of data resulting from PUT and Program Stack operators;
• (h4) a source field for initiating selection of data for:
• (i) an Arithmetic Logic Unit or PUT operation;
• (ii) a GET operation;
• (iii) a Program Stack operation;
• (h5) a bit field for parity information;
• (h6) a single bit field "M" for signaling said decoder-controller to select either said program counter or said memory reference register as an address source for operands of the current instruction;
• (h7) a single bit field "C" for signaling said decoder-controller to initiate or not initiate the said Arithmetic Logic Unit to copy its output into said memory reference register.