I/O Request interrupt mechanism

In a computer system having a microprocessor (.mu.P) for executing channel routines and subroutines, a U-bus coupled to said microprocessor, a main memory, an M-bus coupled to said main memory, a bus-driver coupled to said M-bus and said U-bus for enabling and disabling information flow between said M-bus and said U-bus, an instruction register (I-register) coupled to said U-bus for storing instructions which initiate or obviate interrupt operation and a plurality of communication devices also coupled to said U-bus for generating interrupt requests, an interrupt apparatus for processing interrupt requests, said interrupt apparatus comprising:

• (a) first means for generating signals forming a predetermined address at the end of every channel subroutine;
• (b) second means coupled to said .mu.P for interrupting said .mu.P, said second means being enabled by said predetermined address signals;
• (c) third means for deriving signals forming the next sequential address from said predetermined address, said next sequential address signals used for enabling said I-register to transfer said instructions to said U-bus and for disabling said bus-driver, whereby a normal memory read data path including said M-bus and said bus-driver is disabled;
• and
• (d) fourth means coupled to said I-register and to said plurality of communication devices for intercepting an interrupt request from one of said plurality of communication devices and for forming said instructions in said I-register.