Core memory interface for coupling a processor to a memory having a differing word length

Abstract

An interface circuit for coupling a digital processor to a core memory. The interface circuit accepts as inputs address signals, data signals, and control signals from the processor and output date from the core memory. The output of the interface circuit consists of control signals to control the memory and a parallel digital data word having 2N bits where N is the number of parallel bits transferred by the digital processor during the execution of an instruction to transfer data to or input data from an external device. To store a digital data word in a particular location in the core memory, the digital processor first transfers a digital data word having N bits to a buffer memory which is a part of the interface circuit. Next, the digital processor executes a store in memory instruction. This instruction causes the normal output data, available on a data bus of the digital processor during the execution of such an instruction along with the N data bits previously stored in the buffer memory to be stored in the core memory at an address location specified by the address available on the address bus of the digital processor. To read data from the core memory the digital processor first executes a read from memory instruction. This instruction causes N bits of a data word stored in the specified memory location to be read directly into the digital processor and the remaining N bits of the word to be transferred to the buffer memory. An input data instruction is then executed to transfer the remaining N bits stored in the buffer memory into the digital processor. Using this technique two instructions are required to store the 2N bit data word in the desired memory location. Similarly, two instructions are required to read a 2N bit data word from a specified location in the core memory.

Dependencies are inferred from the claim text.