US 4,291,240 AGranted

Two output clock for integrated semiconductor digital circuits

AssigneeSiemens Aktiengesellschaft

InventorHelmut Rosler

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Abstract

A pulse converter for transforming periodic signals of any waveform into two output series of digital pulses such that the duty cycle of one of the series is temporarily separated from the duty cycle of the other series by non-duty cycle intervals to avoid interfering overlapping of the pulse series when employed in additional digital circuitry as clock pulses. The pulse converter can be attached to any periodic signal input, or may be provided with an input network to produce the pulse series from standard alternating current.

Claims8

Dependent claims

A clock pulse converter for use with integrated semiconductor digital circuits, said converter having an input connected to a periodic signal supply and having two signal outputs at which different digital pulses having the same period appear, said converter comprised of:

an input level circuit having an input resistor connected to said signal supply and having controlled inverted and non-inverted signal outputs;
a first flip-flop cell having two inputs connected to respective ones of said input level circuit outputs and having first and second signal outputs;
two equivalent delay lines each having an input connected to a respective one of said first flip-flop cell outputs, and each having an output;
a second flip-flop cell having two signal inputs each connected to a respective one of said delay line outputs, said second flip-flop cell having a first signal output which in the absence of a delay between the signal inputs of the first flip-flop cell and the signal outputs of the second flip-flop cell would be synchronized with and have the same logical state as the inverted signal input to the first flip-flop cell, said second flip-flop cell also having a second output having the opposite logical state;
a third flip-flop cell having two signal inputs, one of which is connected to said first signal output of said second flip-flop cell and the other of which is connected through an inverter to said signal supply, said third flip-flop cell having two available outputs, only one of which is connected to said input level circuit for controlling the output thereof, said connected third flip-flop cell output changing to a controlling logical state in sequence after the other available output reaches said state;
a first output logic gate having two signal inputs, one of which is connected to said first output of said second flip-flop cell, and the other of which is connected to the output of said first flip-flop cell which, in the absence of the delay lines would be synchronized with and display the same logic level as the first output of said second flip-flop cell, said output logic gate having an output forming one converter output;
and
a second logic output gate having two signal inputs, one of which is connected to the second signal output of the second flip-flop cell, and the other of which is connected to the output of said first flip-flop cell not connected to the first logic output gate, said second logic output gate having an output forming one of the converter outputs.

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Abstract

an input level circuit having an input resistor connected to said signal supply and having controlled inverted and non-inverted signal outputs;
a first flip-flop cell having two inputs connected to respective ones of said input level circuit outputs and having first and second signal outputs;
two equivalent delay lines each having an input connected to a respective one of said first flip-flop cell outputs, and each having an output;
a second flip-flop cell having two signal inputs each connected to a respective one of said delay line outputs, said second flip-flop cell having a first signal output which in the absence of a delay between the signal inputs of the first flip-flop cell and the signal outputs of the second flip-flop cell would be synchronized with and have the same logical state as the inverted signal input to the first flip-flop cell, said second flip-flop cell also having a second output having the opposite logical state;
a third flip-flop cell having two signal inputs, one of which is connected to said first signal output of said second flip-flop cell and the other of which is connected through an inverter to said signal supply, said third flip-flop cell having two available outputs, only one of which is connected to said input level circuit for controlling the output thereof, said connected third flip-flop cell output changing to a controlling logical state in sequence after the other available output reaches said state;
a first output logic gate having two signal inputs, one of which is connected to said first output of said second flip-flop cell, and the other of which is connected to the output of said first flip-flop cell which, in the absence of the delay lines would be synchronized with and display the same logic level as the first output of said second flip-flop cell, said output logic gate having an output forming one converter output;
and
a second logic output gate having two signal inputs, one of which is connected to the second signal output of the second flip-flop cell, and the other of which is connected to the output of said first flip-flop cell not connected to the first logic output gate, said second logic output gate having an output forming one of the converter outputs.

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