Digital semiconductor circuit
AssigneeSiemens Aktiengesellschaft
InventorsOtto Muehlbauer, Klaus D. Bigall, Helmut Roessler
Life of this patent
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Abstract
A digital semiconductor circuit has at least two circuit parts, each including a counting chain having identical memory cells which serve for receiving and transmitting digital information. The counters are controlled by a common clock. The counter of the first circuit part is coupled to a signal generator which emits a digital pulse upon reading a predetermined, specific digital state of the counter of the first part. The signal generator emits a digital pulse which is superposed on a clock pulse so as to amplitude modulate the same. The modulated clock pulse is detected by a signal recognition circuit of the second circuit part to trigger a correction signal generator which sets the counter of the second circuit part to a predetermined count.
Claims16
A digital semiconductor apparatus, comprising:
- a clock for generating standard clock pulses;
- first and second pulse counters each comprising a plurality of memory cells, an input terminal connected to receive clock pulses and a plurality of outputs, each counter operable to count clock pulses applied thereto;
- signal generator means connected between said plurality of outputs of said first counter and said input terminal of said second counter and operable in response to a predetermined count to produce a digital pulse to modulate a pulse onto the clock pulse appearing at the input terminal of said second counter to provide a modulated clock pulse;
- a modulated clock pulse recognition circuit connected to said input terminal of said second counter and operable to produce a recognition signal in response to the occurrence of a modulated clock pulse;
- and
- a correction signal circuit connected between said modulated clock pulse recognition circuit and each of said memory cells of said second counter, and responsive to a recognition signal to set said second counter to a predetermined count.
A method of synchronizing two counters driven by the same clock each of which have a plurality of counting stages and each operable to count clock pulses, comprising the steps of:
- monitoring the count of a first of the counters;
- producing a digital pulse in response to a predetermined count of the monitored counter;
- modulating a clock pulse with said digital pulse;
- triggering a correction signal in resonse to said modulated clock pulse;
- and
- applying the correction signal to the second counter to set the same to a predetermined count.
Dependencies are inferred from the claim text.