Circuit arrangement for monitoring the state of signal systems, particularly traffic light signal systems

A circuit arrangement for monitoring the state of a signal system, comprising:

• a memory means storing a plurality of test signals corresponding to admissible actual states;
• an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state;
• and
• signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual signal with all test signals and emit said predetermined clock pulse sequence in response to inequality of an actual state signal and a test signal.

A circuit arrangement for monitoring the state of a signal system, comprising:

• a memory means storing a plurality of test signals indicating test signal states, said memory means comprising first and second memories each storing a respective group of said test signals;
• an evaluation means including an input and an output and operable in response to a predetermined clock pulse sequence at said input to provide an output signal indicating an inadmissible actual signal state, said evaluation means comprising first and second evaluation devices each including an input for receiving the predetermined clock pulse sequence and an output for indicating an inadmissible actual signal state;
• and
• signal comparison means including first inputs for receiving sequential actual state signals, second inputs connected to said memory means for receiving the test signals and an output connected to said evaluation means, and operable to sequentially compare each actual state signal with all test signals and emit said predetermined clock pulse sequence in response to a comparison indicating an inadmissible actual state, said signal comparison means comprising first and second microprocessors connected to receive respective groups of actual state signals from said first inputs and connected to respective ones of said memories for receiving respective groups of test signals, and first and second program means connected to respective microprocessors for programming said microprocessors to compare the actual and test signals, each of said microprocessors connected to the input of a respective evaluation device.