System timing means for data processing system
AssigneeDigital Equipment Corporation
InventorsRobert E. Stewart, Barry J. Flahive, David Potter
Life of this patent
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Abstract
A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses. A central clocking circuit generates timing signals that control such communications on a synchronous basis. The clocking circuit includes oscillator, control and sequencing circuits that produce phase and clocking signals that are coupled to each nexus. Each nexus contains receivers and decoders for converting the phase and clocking signals into a sequence of internal timing signals that synchronizes the operation of the nexus to transfers among the nexuses.
Claims14
In a data processing system including a processor unit for processing data in response to instructions, at least one other unit for transferring data to and from said processor unit and bus means connected to the units for transferring signals among the units, the improvement of system timing means for controlling the transfer of signals among the units, said system timing means comprising:
- A. clock generator means connected to said bus means for generating timing signals, said clock generator means including:
- i. oscillator means for generating timing reference signals as first timing signals, and
- ii. sequencer means connected to said oscillator means for transmitting a phase signal and a clocking signal in synchronism with the timing reference signals from said oscillator means, and
- B. timing conductor means in the bus connected to said sequencer means in said clock generator means for coupling the phase and clocking signals to the processor and other units, and
- C. timing means in each of the processor and other units for establishing internal timing for each said unit in response to the phase and clocking signals, each said timing means comprising:
- i. decoding means connected to said receiving means for transmitting a sequence of unit timing signals, said decoding means including means for generating each unit timing signal in response to the phase signal and for an interval determined by the clocking signal, whereby the phase signal governs the position of the respective unit timing signals in the sequence, and the clocking signal controls the duration of each of the respective unit timing signals, the unit timing signals in a given unit controlling the functions that the unit performs.
A unit that connects to a bus in a data processing system and that transfers data to and from the bus means wherein the bus means connects to other units for transferring signals among the units and includes timing conductor means and wherein the data processing system further includes oscillator means for generating timing reference signals and sequencer means connected to the oscillator means for transmitting onto the timing conductor means plural phase control signals and a clocking signal in synchronism with the timing reference signals from said oscillator means, said unit comprising:
- A. receiving means connected to the timing conductor means for receiving the phase control and clocking signals, and
- B. decoding means connected to said receiving means for transmitting a sequence of unit timing signals, said decoding means including means for generating each unit timing signal in response to the phase control signal for an interval determined by the clocking signal, whereby the phase control signals govern the position of the respective unit timing signals in the sequence and the clocking signal controls the duration of each of the respective unit timing signals, the unit timing signals being changed in response to the clocking signal from the receiving means, and
- C. function means connected to said decoding means for affecting a data transfer in response to the sequence of unit timing signals.
Dependencies are inferred from the claim text.