Microprocessor system with source address selection

A universal-type microprocessor system which cooperates with an application-dependent logic module to form a peripheral-controller capable of handling data transfers between main memory of a host computer and a plurality of peripheral terminal units which can be either "word-oriented" or "byte-oriented", and wherein said application-dependent logic module provides external register means having bus connections to said plurality of peripheral terminal units and to said host computer, and wherein said application-dependent logic module further includes an external memory for storage of programs related to control of said peripheral terminal units and for temporary storage of data undergoing transfer, and wherein said application-dependent logic module further includes control logic means for communicating with and controlling:

• said external register means, said external memory and communicating with a decoder-controller in said microprocessor system, the said microprocessor system comprising:
• (a) data processing means including:
• (a1) an Arithmetic logic Unit providing an output to a shift logic circuit and to a byte-swap circuit;
• (a2) a shift logic circuit providing output to an I/O bus;
• (a3) a byte-swap circuit providing output to said I/O bus;
• (b) an I/O bus providing connecting lines from said data processing means to said external registers, to said external memory, to an accumulator register means, and to an addressing means;
• (c) addressing means receiving input data from said I/O bus and storing addresses used for accessing data from internal or external memory, said addressing means including:
• (c1) a program counter storing consecutive addresses of data located in an internal program memory;
• (c2) a memory reference register for storing addresses of data located in said external memory, and including:
• (c2-1) a memory address bus which connects to said external memory;
• (c3) an address register means in said decoder-controller and providing an address bus to a plurality of accumulator registers for selection of data from/to an addressed accumulator register;
• (d) internal program memory for storing program instructions and data words, said internal memory being addressed from said program counter and providing instruction words and data, via an instruction bus, to a register means.
• (e) register means for temporary storage of data, said register means including:
• (e1) a plurality of addressable accumulator registers which provide an output to the input of said Arithmetic Logic Unit, said accumulator registers receiving input data words from said I/O bus, said plurality of accumulator registers, including:
• (e1-1) address bus means from said decoder-controller for addressing selected registers in said plurality of accumulator registers;
• (e2) a memory operand register for receiving operand data from said internal program memory via an instruction bus or from said external memory via a memory data bus;
• said operand register providing an output to the input of said Arithmetic Logic Unit;
• (e3) an instruction register for receiving instruction words and data from said internal program memory via said instruction bus or receiving data from said external memory via a memory data bus and providing instruction words and data to said decoder-controller;
• (f) an instruction decoder-controller receiving instruction signals from said instruction register, and including incoming and outgoing control signal lines connected to said data processing means, to said addressing means, to said register means, to said internal and external memory means, to said external registers and said control logic means;
• (g) an external memory data bus for carrying data from said external memory to said instruction register and said memory operand register.
• (h) program instruction words in said internal program memory wherein each instruction word includes a bit field "M" which is used to signal said decoder-controller to select either said program counter or said memory reference register as the next address source for data to be transmitted to said instruction register or said memory operand register.