High speed phase locked loop frequency synthesizer
AssigneeInternational Telephone and Telegraph Corporation
InventorJesse S. LeGrand
Life of this patent
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Abstract
A phase locked looped type frequency synthesizer utilizing a source of a reference signal comprising a voltage controlled oscillator and a phase detector which receives the reference signal and compares that to the output signal of the voltage control oscillator after suitable division by a programmable divider. The phase detector outputs a control voltage to the oscillator thereby regulating the output frequency from the oscillator wherein the programmable divider is programmed to divide or count by N, where N is capable of being a division number which is an integer or non-integer thereby allowing an increasing of the reference frequency and a decreasing of the settling time of the system without a need to increase the channel spacing.
Claims19
A phase locked loop type frequency synthesizer comprising:
- a reference signal source;
- a division factor program source providing a predetermined selected digital number N represented by a plurality of digital bits;
- a voltage controlled oscillator (VCO) having an input and an output to provide an output signal for said synthesizer;
- a phase detector having a first input coupled to said reference signal source, an output coupled to said input of said VCO and a second input;
- a programmable divider having a first input coupled to said program source, a second input coupled to said output of said VCO and an output coupled to said second input of said phase detector, said divider being responsive to said predetermined number N for dividing said synthesizer output signal by a given division number M, where M is equal to N/x when said predetermined number N is even and is equal alternately to (N-1)/x and (N+1)/x when said predetermined number N is odd, where x is an integer less than said predetermined number N;
- and
- first means coupled to said output of said divider and said program source responsive to a given one of said plurality of bits of said predetermined number N to control said divider so that the average value of said given number M can be a non-integer.
Dependencies are inferred from the claim text.