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US 4,290,015 AGranted
Electrical validator for a printed circuit board test fixture and a method of validation thereof
AssigneeFairchild Camera and Instrument Corporation
InventorDonald J. Labriola
Life of this patent
Estimating the term…
Abstract
This invention relates to a structure for testing the integrity of a printed circuit board test fixture and to a method for implementing the verification of the fixture.
Claims9
A structure for validating the performance of a test fixture for a test system for printed circuit boards, the structure comprising:
- a board having (1) an electrically conductive sheet on a first region of a surface of the board and (2) a plurality of electrically conductive pads on a second region of the surface, the pads electrically isolated from each other and from the sheet, the board having no transistors formed on it;
- and
- a test module having (1) a like plurality of first output leads corresponding on a one-to-one basis to the pads, each first lead attached to the corresponding pad, (2) a second output lead attached to the sheet, and (3) a like plurality of impedance elements corresponding on a one-to-one basis to the first leads, each impedance element connected between the second lead and the corresponding first lead.
A method of validating a printed circuit board test fixture having contact probes to ensure proper operation of the test fixture comprising the steps of:
- placing each probe in intended contact with a board having an electrically conductive sheet on a surface thereof but having no transistors formed thereon;
- sequentially passing an electrical signal through each probe, the sheet, and a selected known impedance to measure the impedance to passage of the signal;
- and
- comparing the measured impedance to an expected impedance, thereby to provide an indication of whether the probe is properly conducting the signal.
1 more element
Dependencies are inferred from the claim text.