Circuit arrangement for the transmission of digital data
AssigneeRobert Bosch GmbH
InventorHans-Peter Maly
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Abstract
A circuit arrangement is described for the transmission of a digital data signal. The circuit arrangement is inserted as an asynchronous interface into the transmission path between digital data handling systems with differing clock frequencies f.sub.1 and f.sub.2. The circuit arrangement comprises a register 1 of D flip-flops for buffering the input data D.sub.1. The clocking of the register 1 is performed with a special clock signal f.sub.Inter, which is derived from a series circuit of edge controlled R-S and J-K flip-flops 3 and 4 respectively. The result is output data D.sub.2 synchronous with the frequency f.sub.2.
Claims4
An interface circuit for the transmission of digital data between digital data handling systems operating with different clock frequencies, the circuit comprising an edge-controlled R-S flip-flop of which the S input is supplied with a first clock signal and the R input is supplied with a second clock signal, a J-K flip-flop of which the J input is maintained at a high logic level and the K input is maintained at a low logic level, the J-K flip-flop having a clock input connected to the output of the R-S flip-flop and a reset input supplied with the second clock signal, and at least one D flip-flop having a clock input connected to the output of the J-K flip-flop and whose D input is arranged to receive digital data at the frequency of the first clock signal, whereby at the output of the D flip-flop digital data is produced in synchronism with the second clock signal.
Dependencies are inferred from the claim text.