Time-period comparing device

A time-period comparing device, for comparing the time-period of an input signal with the time-period of a reference signal comprising:

• a reference oscillator for producing a pulse signal;
• a reference period counter, operatively connected to said reference oscillator, for receiving said pulse signal as a clock signal thereof, for receiving the input signal as a reset signal thereof, and for producing the reference signal from an inverting output thereof, the reference signal being either a first rectangular wave signal or a first high logic level signal in dependence upon the time-period of the input signal;
• a time-period comparator, operatively connected to said reference period counter, for receiving the input signal and the reference signal and for providing a device output signal in dependence upon the relationship between the time-period of the reference signal and the time-period of the input signal,
• said time-period comparator including a first counter, operatively connected to said reference period counter, and operatively connected to receive the input signal as a clock signal thereof, for receiving the reference signal as a reset signal thereof, and for providing an inverting output signal, said inverting output signal being either a second high logic level signal or a second rectangular wave signal in dependence upon the time-period of the input signal;
• said time-period comparator further including a latch circuit, having two inputs connected to an inverting output of said first counter and to said inverting output of said reference period counter, respectively, for receiving said inverting output signal and the reference signal, respectively, and for providing said device output signal, whereby said latch circuit has two different states corresponding to the relationship between the time-period of the input signal and the time-period of the reference signal.

A time-period comparing device, for comparing the time-period of an input signal with the time-period of a reference signal, comprising:

• a reference oscillator for providing a pulse signal;
• a reference period counter, operatively connected to said reference oscillator, for receiving said pulse signal as a clock signal, for receiving the input signal as a reset signal thereof, and for producing the reference signal from an inverting output, the reference signal being either a first rectangular wave signal or a first high logical level signal in dependence upon the time-period of the input signal;
• a time-period comparator, operatively connected to said reference period counter, for receiving the input signal and the reference signal and for providing a device output signal in dependence upon the relationship between the time-period of the reference signal and the time-period of the input signal,
• said time-period comparator including a first counter, operatively connected to said reference period counter, for receiving the input signal as a clock signal thereof, for receiving the reference signal as a reset signal thereof, and for providing an inverting output signal, said inverting output signal being either a second high logical level signal or a second rectangular wave signal in dependence upon the time-period of the input signal;
• said time-period comparator further including a first latch circuit, having two inputs connected to an inverting output of said first counter and to said inverting output of said reference period counter for receiving said inverting output signal and the reference signal, respectively, and for providing said device output signal, whereby said first latch circuit has two different states corresponding to the relationship between the time-period of the input signal;
• preventing means, operatively connected to said reference period counter and said time-period comparator, for preventing said device from operating when the input signal is an irregular signal, said preventing means including a first logic gate circuit operatively connected to said first latch circuit, a second logic gate circuit operatively connected to said first latch circuit, a third logic gate circuit operatively connected to said first latch circuit, an n-ary counter circuit operatively connected to said first, second and third logic gate circuits and a second latch circuit operatively connected to said third logic gate circuit, an output of which serves as an output of said device, said n-ary counter being reset by another signal passed through said second logic gate circuit when the state of said first latch circuit is inverted and counting rear edges of said input signal or said first rectangular signal, the state of said second latch circuit being inverted only when the value of said n-ary counter is (n-1).

A time-period comparing device, for comparing the time-period of an input signal with the time-period of a reference signal comprising:

• a reference oscillator for producing a pulse signal,
• a reference period counter, operatively connected to said reference oscillator, for receiving said pulse signal as a clock signal, for receiving the input signal as a reset signal thereof, and for producing the reference signal from an inverting output, the reference signal being either a first rectangular wave signal or a first high level signal in dependence upon the time-period of the input signal;
• a time-period comparator, operatively connected to said reference period counter, for receiving the input signal and the reference signal and for providing a device output signal in dependence upon the relationship between the time-period of the reference signal and the time-period of the input signal,
• said time-period comparator including a first counter, operatively connected to said reference period counter, for receiving the input signal as a clock signal, for receiving the reference signal as a reset signal thereof, and for providing an inverting output signal from said first counter, said inverting output signal being either a second high level signal or a second rectangular wave signal in dependence upon the time-period of the input signal;
• said time-period comparator further including a first latch circuit, having two inputs connected to an inverting output of said counter and to said inverting output of said reference period counter, respectively, and for providing said device output signal, whereby said first latch circuit has two different states corresponding to the relationship between the time-period of the input signal and the time period of the reference signal;
• preventing means, operatively connected to said reference period counter and said time-period comparator, for preventing said device from operating when the input signal is an irregular signal, said preventing means including a first logic gate circuit operatively connected to said first latch circuit, a second logic gate circuit operatively connected to said first latch circuit, a third logic gate circuit operatively connected to said first latch circuit, and n-ary counter circuit operatively connected to said first, second and third logic gate circuits and a second latch circuit operatively connected to said third logic gate circuit, an output of which serves as an output of said device, said n-ary counter being reset by another signal passed through said second logic gate circuit when the state of said first latch circuit is inverted and counting rear edges of said input signal or said first rectangular signal, the state of said second latch circuit being inverted only when the value of said n-ary counter is (n-1);
• stopping means, operatively connected to said reference period counter, for preventing said device from operating for a definite interval after the power is turned on, said stopping means including a second counter for counting pulses generated by said reference oscillator through said reference counter, said stopping means further including a third latch circuit, having two inputs connected to an inverting output and a reset terminal of said second counter;
• initial reset means operatively connected to said reference period counter and said second counter for resetting said reference period counter and said second counter at a time after the power is turned on;
• an inverted input OR gate for producing an output signal of said device, said inverted input OR gate connected to outputs of said second latch circuit and said third latch circuit, whereby said inverted input OR gate is in a closed state for said definite interval.