Method for qualifying biased integrated circuits on a wafer level
AssigneeHarris Corporation
InventorKenneth A. Ports
Life of this patent
Estimating the term…
Abstract
Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.
Claims23
A method for qualifying radiation hard integrated circuits at the wafer level comprising:
- electrically interconnecting the dice containing said integrated circuits on the wafer electrically;
- electrically biasing the dice on said wafer;
- irradiating the wafer with gamma ray radiation while said dice are electrically biased;
- annealing said dice sufficiently to remove radiation damage;
- and
- testing the circuitry on said dice.
A method for qualifying radiation hard integrated circuits at the wafer level comprising:
- forming a first and second electrode each having a plurality of conductors on said wafer, each die on said wafer containing an integrated circuit being connected to a conductor of both of said electrodes;
- electrically biasing said first and second electrodes;
- irradiating the wafer with gamma ray radiation while said dice are electrically biased;
- removing said conductors;
- testing the circuitry on said dice and marking defective dice;
- and
- annealing said dice sufficiently to remove radiation damage.
A method for qualifying radiation hard integrated circuits at the wafer level comprising;
- forming a first and a second discrete conductor on said wafer, each connected to each die containing an integrated circuit on said wafer, at least one of said conductors being connected to each die by a fusible element;
- electrically biasing said conductors;
- irradiating the wafer while said dice are electrically biased;
- annealing said dice sufficiently to remove radiation damage;
- and
- testing the circuitry on said dice.
A method for qualifying integrated circuits at the wafer level comprising:
- forming a first and a second discrete conductor on said wafer, each connected to each die containing an integrated circuit on said wafer, at least one of said conductors being connected to each die by a fusible element;
- electrically biasing said conductors;
- subjecting said wafer to the qualifying environment while said dice are electrically biased;
- testing the condition of said fusible elements and marking disconnected dice;
- and
- testing the circuitry on said dice and marking defective dice.
Dependencies are inferred from the claim text.