Timing data reproduction system
AssigneeRicoh Company, Ltd.
InventorKunihiro Yamada
Life of this patent
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Abstract
A system for generating from the incoming digital data signal the timing data required for sampling the data signal. A shift register is provided to phase the sampling clock with the incoming digital signal and generate a phase difference signal which is applied to a variable-frequency or variable phase oscillator so as to control its output frequency or phase, thereby synchronizing the sampling clock pulse with the incoming data signal. The output from the oscillator is used as the sampling clock.
Claims8
A system for providing a sampling clock reference signal for information encoded in a digital data signal having a given pulse repetition rate and pulse width, comprising:
- means including a variable frequency or phase oscillator for sampling said digital data signal at successive time intervals determined by the frequency of the oscillator output signal, said frequency being on the order of twice said given pulse repetition rate, so that said sampling time intervals are on the order of one-half said digital data signal pulse width;
- a shift register coupled to said sampling means for storing successive groups of samples of said digital data signal, each group comprising at least two successive samples thereof;
- oscillator control means including a logic circuit for converting the pattern of digital data signal samples stored in said shift register into a control signal, the value of which is indicative of whether the phase of said digital data signal leads or lags the phase of said oscillator,
- said oscillator control means further including means for varying the frequency or phase of the output signal of said oscillator in accordance with said control signal so that the phase of said oscillator is maintained in coincidence with the phase of said digital data signals;
- and
- frequency divider means for synchronously dividing the frequency of the oscillator output signal in half to provide said sampling clock reference signal.
Dependencies are inferred from the claim text.